freedev_cycloneii_50.fit.rpt

verilog 代码

; Timing Models                      ; Preliminary                              ;
; Total logic elements               ; 1,459 / 33,216 ( 4 % )                   ;
; Total pins                         ; 52 / 322 ( 16 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 169,984 / 483,840 ( 35 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Option                                         ; Setting                        ; Default Value                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Device                                         ; EP2C35F484C8                   ;                                ;
; Use smart compilation                          ; Off                            ; Off                            ;
; Placement Effort Multiplier                    ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                       ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                           ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                    ; Off                            ; Off                            ;
; Optimize Timing                                ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing     ; On                             ; On                             ;
; Limit to One Fitting Attempt                   ; Off                            ; Off                            ;
; Final Placement Optimizations                  ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                  ; 1                              ; 1                              ;
; PCI I/O                                        ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                          ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                      ; Off                            ; Off                            ;
; Auto Global Memory Control Signals             ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto                           ; Auto                           ;
; Auto Delay Chains                              ; On                             ; On                             ;
; Auto Merge PLLs                                ; On                             ; On                             ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
+------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+----------------------------------------------+-----------------------------------------+
; Option                                       ; Setting                                 ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                                     ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                     ;
; Enable device-wide output enable (DEV_OE)    ; Off                                     ;
; Enable INIT_DONE output                      ; Off                                     ;
; Configuration scheme                         ; Active Serial                           ;
; Error detection CRC                          ; Off                                     ;
; Reserve nCEO pin after configuration         ; As output driving ground                ;
; Reserve ASDO pin after configuration.        ; As output driving an unspecified signal ;
; Reserve all unused pins                      ; As input tri-stated                     ;
; Base pin-out file on sameframe device        ; Off                                     ;
+----------------------------------------------+-----------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                               ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node                                                                                                                                             ; Action          ; Operation        ; Reason                                 ; Node Port ; Destination Node                                                                                                                           ; Destination Port ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[15]    ; Packed Register ; Register Packing ; Fast Input Register assignment         ; REGOUT    ; D[15]                                                                                                                                      ; COMBOUT          ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[14]    ; Packed Register ; Register Packing ; Fast Input Register assignment         ; REGOUT    ; D[14]                                                                                                                                      ; COMBOUT          ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[13]    ; Packed Register ; Register Packing ; Fast Input Register assignment         ; REGOUT    ; D[13]                                                                                                                                      ; COMBOUT          ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[12]    ; Packed Register ; Register Packing ; Fast Input Register assignment         ; REGOUT    ; D[12]                                                                                                                                      ; COMBOUT          ;