freedev_cycloneii_50.map.rpt

verilog 代码

+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+--------------------------------------------------------------------+--------------------------+----------------------+
; Option                                                             ; Setting                  ; Default Value        ;
+--------------------------------------------------------------------+--------------------------+----------------------+
; Device                                                             ; EP2C35F484C8             ;                      ;
; Top-level entity name                                              ; freedev_cycloneII_50_top ; freedev_cycloneII_50 ;
; Family name                                                        ; Cyclone II               ; Stratix              ;
; Use smart compilation                                              ; Off                      ; Off                  ;
; Restructure Multiplexers                                           ; Auto                     ; Auto                 ;
; Create Debugging Nodes for IP Cores                                ; off                      ; off                  ;
; Preserve fewer node names                                          ; On                       ; On                   ;
; Disable OpenCore Plus hardware evaluation                          ; Off                      ; Off                  ;
; Verilog Version                                                    ; Verilog_2001             ; Verilog_2001         ;
; VHDL Version                                                       ; VHDL93                   ; VHDL93               ;
; State Machine Processing                                           ; Auto                     ; Auto                 ;
; Extract Verilog State Machines                                     ; On                       ; On                   ;
; Extract VHDL State Machines                                        ; On                       ; On                   ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                       ; On                   ;
; DSP Block Balancing                                                ; Auto                     ; Auto                 ;
; Maximum DSP Block Usage                                            ; -1                       ; -1                   ;
; NOT Gate Push-Back                                                 ; On                       ; On                   ;
; Power-Up Don't Care                                                ; On                       ; On                   ;
; Remove Redundant Logic Cells                                       ; Off                      ; Off                  ;
; Remove Duplicate Registers                                         ; On                       ; On                   ;
; Ignore CARRY Buffers                                               ; Off                      ; Off                  ;
; Ignore CASCADE Buffers                                             ; Off                      ; Off                  ;
; Ignore GLOBAL Buffers                                              ; Off                      ; Off                  ;
; Ignore ROW GLOBAL Buffers                                          ; Off                      ; Off                  ;
; Ignore LCELL Buffers                                               ; Off                      ; Off                  ;
; Ignore SOFT Buffers                                                ; On                       ; On                   ;
; Limit AHDL Integers to 32 Bits                                     ; Off                      ; Off                  ;
; Optimization Technique -- Cyclone II                               ; Balanced                 ; Balanced             ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                       ; 70                   ;
; Auto Carry Chains                                                  ; On                       ; On                   ;
; Auto Open-Drain Pins                                               ; On                       ; On                   ;
; Remove Duplicate Logic                                             ; On                       ; On                   ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                      ; Off                  ;
; Perform gate-level register retiming                               ; Off                      ; Off                  ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                       ; On                   ;
; Auto ROM Replacement                                               ; On                       ; On                   ;
; Auto RAM Replacement                                               ; On                       ; On                   ;
; Auto Shift Register Replacement                                    ; On                       ; On                   ;
; Auto Clock Enable Replacement                                      ; On                       ; On                   ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On                       ; On                   ;
; Auto Resource Sharing                                              ; Off                      ; Off                  ;
; Allow Any RAM Size For Recognition                                 ; Off                      ; Off                  ;
; Allow Any ROM Size For Recognition                                 ; Off                      ; Off                  ;
; Allow Any Shift Register Size For Recognition                      ; Off                      ; Off                  ;
; Maximum Number of M4K Memory Blocks                                ; -1                       ; -1                   ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                      ; Off                  ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                       ; On                   ;
+--------------------------------------------------------------------+--------------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; freedev_cycloneII_50_top.bdf     ; yes             ; User Block Diagram/Schematic File  ; J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf   ;
; freedev_cycloneII_50.v           ; yes             ; Other                              ; J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v         ;
; asmi.v                           ; yes             ; Other                              ; J:/board/freedev_cycloneII_50/system/asmi.v                         ;
; cpu_0.v                          ; yes             ; Encrypted File                     ; J:/board/freedev_cycloneII_50/system/cpu_0.v                        ;
; cpu_0_test_bench.v               ; yes             ; Other                              ; J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v             ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf          ;
; stratix_ram_block.inc            ; yes             ; Other                              ; c:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc   ;
; lpm_mux.inc                      ; yes             ; Other                              ; c:/altera/quartus50/libraries/megafunctions/lpm_mux.inc             ;