freedev_cycloneii_50.map.rpt

verilog 代码

Analysis & Synthesis report for freedev_cycloneII_50
Fri Aug 11 17:53:33 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Protected by SYN_PRESERVE, DONT_TOUCH
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
 13. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
 14. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram
 15. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram
 16. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
 17. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
 18. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
 19. Parameter Settings for User Entity Instance: freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
 20. Parameter Settings for User Entity Instance: delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
 21. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 22. scfifo Parameter Settings by Entity Instance
 23. Analysis & Synthesis Equations
 24. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Aug 11 17:53:33 2006    ;
; Quartus II Version                 ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name                      ; freedev_cycloneII_50                     ;
; Top-level Entity Name              ; freedev_cycloneII_50_top                 ;
; Family                             ; Cyclone II                               ;
; Total combinational functions      ; 1380                                     ;
; Total registers                    ; 768                                      ;
; Total pins                         ; 56                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 169,984                                  ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+