bidir.v

来自「verilog HDL example .many module .」· Verilog 代码 · 共 8 行

module bidir(tri_inout,out,in,en,b);
inout tri_inout;
output out;
input in,en,b;
assign tri_inout = en ? in : 'bz;
assign out = tri_inout ^ b;
endmodule