div_clk.vhd

主时钟为15.36MHz的带选通的8位输出分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV12 IS
PORT(CLK,RST:IN STD_LOGIC;
     CLK_12D:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE behav OF DIV12 IS
SIGNAL TEMP:STD_LOGIC;
BEGIN
PROCESS(CLK,RST)
VARIABLE COUNT12D:INTEGER RANGE 0 TO 15;
CONSTANT SIGN:INTEGER:=5;
BEGIN
IF (RST='1')THEN 
  TEMP<='0';
 ELSIF RISING_EDGE(CLK) THEN
  IF(COUNT12D=SIGN)THEN
    COUNT12D:=0;
    TEMP<=NOT TEMP;
  ELSE
    COUNT12D:=COUNT12D+1;
  END IF;
END IF;
END PROCESS;
CLK_12D<=TEMP;
END behav;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV10 IS
PORT(CLK,RST:IN STD_LOGIC;
     CLK_10D:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE behav OF DIV10 IS
SIGNAL TEMP:STD_LOGIC;
BEGIN
PROCESS(CLK,RST)
VARIABLE COUNT10D:INTEGER RANGE 0 TO 15;
CONSTANT SIGN:INTEGER:=4;
BEGIN
IF (RST='1')THEN 
  TEMP<='0';
 ELSIF RISING_EDGE(CLK) THEN
  IF(COUNT10D=SIGN)THEN
    COUNT10D:=0;
    TEMP<=NOT TEMP;
  ELSE
    COUNT10D:=COUNT10D+1;
  END IF;
END IF;
END PROCESS;
CLK_10D<=TEMP;
END behav;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLK_2D IS
PORT(CLK,RST:IN STD_LOGIC;
     CLK_ID:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END CLK_2D;
ARCHITECTURE behav OF CLK_2D IS
SIGNAL COUNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK,RST)
BEGIN
IF (RST='1')THEN 
  COUNT<="00000000";
ELSIF RISING_EDGE(CLK) THEN
  IF(COUNT="11111111")THEN
    COUNT<=(OTHERS=>'0');
  ELSE
    COUNT<=COUNT+'1';
  END IF;
END IF;
END PROCESS;
CLK_ID(0)<=CLK;
CLK_ID(1)<=COUNT(0);
CLK_ID(2)<=COUNT(1);
CLK_ID(3)<=COUNT(2);
CLK_ID(4)<=COUNT(3);
CLK_ID(5)<=COUNT(4);
CLK_ID(6)<=COUNT(5);
CLK_ID(7)<=COUNT(6);
END behav;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLK_DIV IS
PORT(CLK,RST:IN STD_LOGIC;
     S1,S0:IN STD_LOGIC;
     DIV_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
ARCHITECTURE behav OF CLK_DIV IS
SIGNAL CLK_DIV1,CLK_DIV2,CLK_DIV3,CLK_DIV4:STD_LOGIC;
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL TEMP1:STD_LOGIC_VECTOR(0 TO 2);
SIGNAL TEMP2:STD_LOGIC_VECTOR(0 TO 3);
SIGNAL DIV_OUT_TEMP:STD_LOGIC;
COMPONENT DIV10 
PORT(CLK,RST:IN STD_LOGIC;
     CLK_10D:OUT STD_LOGIC);
END COMPONENT;
COMPONENT DIV12 
PORT(CLK,RST:IN STD_LOGIC;
     CLK_12D:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CLK_2D
PORT(CLK,RST:IN STD_LOGIC;
     CLK_ID:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
BEGIN
U0:DIV12 PORT MAP(CLK=>CLK,RST=>RST,CLK_12D=>TEMP1(0));
G1:FOR I IN 0 TO 1 GENERATE 
   DIV10X:DIV10 PORT MAP(CLK=>TEMP1(I),RST=>RST,CLK_10D=>TEMP1(I+1));
   END GENERATE G1;
   CLK_DIV4<=TEMP1(0);
   CLK_DIV3<=TEMP1(1);
   CLK_DIV1<=TEMP1(2);
   TEMP2(0)<=CLK;
G2:FOR I IN 0 TO 2 GENERATE
   DIV10XX:DIV10 PORT MAP(CLK=>TEMP2(I),RST=>RST,CLK_10D=>TEMP2(I+1));
   END GENERATE G2;
   CLK_DIV2<=TEMP2(3);
U1:CLK_2D PORT MAP(CLK=>DIV_OUT_TEMP,RST=>RST,CLK_ID=>DIV_OUT);
PROCESS(SEL,S0,S1,CLK_DIV1,CLK_DIV2,CLK_DIV3,CLK_DIV4)
BEGIN
  SEL<=S1&S0;
  CASE SEL IS 
    WHEN"00"=>DIV_OUT_TEMP<=CLK_DIV1;
    WHEN"01"=>DIV_OUT_TEMP<=CLK_DIV2;
    WHEN"10"=>DIV_OUT_TEMP<=CLK_DIV3;
    WHEN"11"=>DIV_OUT_TEMP<=CLK_DIV4;
    WHEN OTHERS=>NULL;
  END CASE;
END PROCESS;
END behav;