singt1.vhd

来自「采用vhdl语言编程」· VHDL 代码 · 共 47 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY singt1 IS
	PORT
	(
		CLK			:	IN 	STD_LOGIC;	--//信号源时钟
		DOUT		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)	--//8位波形数据输出
	);
END;

ARCHITECTURE DACC OF singt1 IS
	COMPONENT data_rom	--//调用波形数据存储器LPM_ROM文件：data_rom.vhd
		PORT
		(
			address		:	IN	STD_LOGIC_VECTOR(5 DOWNTO 0);	--//6位地址信号
			inclock		:	IN	STD_LOGIC;						--//地址锁存时钟
			q			:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
	END COMPONENT;

		SIGNAL Q1 : STD_LOGIC_VECTOR(5 DOWNTO 0);	--//内部节点作为地址计数器
		SIGNAL NewCLK: STD_LOGIC;
		SIGNAL CLK_CNT:STD_LOGIC_VECTOR(4 DOWNTO 0);
		
	BEGIN
		NewCLK	<=	CLK_CNT(4);		
		---------------------------
		PROCESS (CLK)
		BEGIN
			IF CLK'EVENT AND CLK= '1' THEN
				CLK_CNT	<=	CLK_CNT+1;
			END IF;
		END PROCESS;
		---------------------------
		PROCESS (NewCLK)
		BEGIN
			IF NewCLK'EVENT AND NewCLK= '1' THEN
				Q1<=Q1+1;
			END IF;
		END PROCESS;

	u1:data_rom PORT MAP(address=>Q1,q=>DOUT,inclock=>CLK);--//例化
END DACC;