singt1.fit.smsg

来自「采用vhdl语言编程」· SMSG 代码 · 共 69 行

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 21 10:38:53 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off singt1 -c singt1
Info: Selected device EP1C6Q240C8 for design "singt1"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 153
Info: Automatically promoted signal "altera_internal_jtag~TCKUTAP" to use Global clock
Info: Automatically promoted some destinations of signal "singt1:inst|CLK_CNT[4]" to use Global clock
    Info: Destination "singt1:inst|CLK_CNT[4]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "sld_signaltap:auto_signaltap_0|reset_all" to use Global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|CLR_SIGNAL" to use Global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|reset_all" may be non-global or may not use global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" to use Global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" may be non-global or may not use global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]" may be non-global or may not use global clock
Info: Automatically promoted signal "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0" to use Global clock
Info: Automatically promoted signal "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is memory to register delay of 6.599 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y3; Fanout = 1; MEM Node = 'sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_lji2:auto_generated|ram_block1a7~portb_address_reg11'
    Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y3; Fanout = 1; MEM Node = 'sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_lji2:auto_generated|ram_block1a7'
    Info: 3: + IC(1.675 ns) + CELL(0.607 ns) = 6.599 ns; Loc. = LAB_X14_Y11; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7]'
    Info: Total cell delay = 4.924 ns ( 74.62 % )
    Info: Total interconnect delay = 1.675 ns ( 25.38 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 12%
    Info: The peak interconnect region extends from location X12_Y11 to location X23_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Node sld_signaltap:auto_signaltap_0|reset_all uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[5] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[1] -- routed using non-global resources
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 179 megabytes of memory during processing
    Info: Processing ended: Tue Oct 21 10:39:01 2008
    Info: Elapsed time: 00:00:08