singt1.map.eqn

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--G1_q_b[1] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[1]
G1_q_b[1]_PORT_A_data_in = VCC;
G1_q_b[1]_PORT_A_data_in_reg = DFFE(G1_q_b[1]_PORT_A_data_in, G1_q_b[1]_clock_0, , , );
G1_q_b[1]_PORT_B_data_in = H1_ram_rom_data_reg[1];
G1_q_b[1]_PORT_B_data_in_reg = DFFE(G1_q_b[1]_PORT_B_data_in, G1_q_b[1]_clock_1, , , );
G1_q_b[1]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[1]_PORT_A_address_reg = DFFE(G1_q_b[1]_PORT_A_address, G1_q_b[1]_clock_0, , , );
G1_q_b[1]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[1]_PORT_B_address_reg = DFFE(G1_q_b[1]_PORT_B_address, G1_q_b[1]_clock_1, , , );
G1_q_b[1]_PORT_A_write_enable = GND;
G1_q_b[1]_PORT_A_write_enable_reg = DFFE(G1_q_b[1]_PORT_A_write_enable, G1_q_b[1]_clock_0, , , );
G1_q_b[1]_PORT_B_write_enable = H1L2;
G1_q_b[1]_PORT_B_write_enable_reg = DFFE(G1_q_b[1]_PORT_B_write_enable, G1_q_b[1]_clock_1, , , );
G1_q_b[1]_clock_0 = clk;
G1_q_b[1]_clock_1 = !A1L6;
G1_q_b[1]_PORT_B_data_out = MEMORY(G1_q_b[1]_PORT_A_data_in_reg, G1_q_b[1]_PORT_B_data_in_reg, G1_q_b[1]_PORT_A_address_reg, G1_q_b[1]_PORT_B_address_reg, G1_q_b[1]_PORT_A_write_enable_reg, G1_q_b[1]_PORT_B_write_enable_reg, , , G1_q_b[1]_clock_0, G1_q_b[1]_clock_1, , , , );
G1_q_b[1] = G1_q_b[1]_PORT_B_data_out[0];


--G1_q_a[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_a[0]_PORT_A_data_in = VCC;
G1_q_a[0]_PORT_A_data_in_reg = DFFE(G1_q_a[0]_PORT_A_data_in, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_B_data_in = H1_ram_rom_data_reg[0];
G1_q_a[0]_PORT_B_data_in_reg = DFFE(G1_q_a[0]_PORT_B_data_in, G1_q_a[0]_clock_1, , , );
G1_q_a[0]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[0]_PORT_A_address_reg = DFFE(G1_q_a[0]_PORT_A_address, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[0]_PORT_B_address_reg = DFFE(G1_q_a[0]_PORT_B_address, G1_q_a[0]_clock_1, , , );
G1_q_a[0]_PORT_A_write_enable = GND;
G1_q_a[0]_PORT_A_write_enable_reg = DFFE(G1_q_a[0]_PORT_A_write_enable, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_B_write_enable = H1L2;
G1_q_a[0]_PORT_B_write_enable_reg = DFFE(G1_q_a[0]_PORT_B_write_enable, G1_q_a[0]_clock_1, , , );
G1_q_a[0]_clock_0 = clk;
G1_q_a[0]_clock_1 = !A1L6;
G1_q_a[0]_PORT_A_data_out = MEMORY(G1_q_a[0]_PORT_A_data_in_reg, G1_q_a[0]_PORT_B_data_in_reg, G1_q_a[0]_PORT_A_address_reg, G1_q_a[0]_PORT_B_address_reg, G1_q_a[0]_PORT_A_write_enable_reg, G1_q_a[0]_PORT_B_write_enable_reg, , , G1_q_a[0]_clock_0, G1_q_a[0]_clock_1, , , , );
G1_q_a[0] = G1_q_a[0]_PORT_A_data_out[0];

--G1_q_b[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[0]
G1_q_b[0]_PORT_A_data_in = VCC;
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , );
G1_q_b[0]_PORT_B_data_in = H1_ram_rom_data_reg[0];
G1_q_b[0]_PORT_B_data_in_reg = DFFE(G1_q_b[0]_PORT_B_data_in, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , );
G1_q_b[0]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = GND;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , );
G1_q_b[0]_PORT_B_write_enable = H1L2;
G1_q_b[0]_PORT_B_write_enable_reg = DFFE(G1_q_b[0]_PORT_B_write_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = clk;
G1_q_b[0]_clock_1 = !A1L6;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, G1_q_b[0]_PORT_B_data_in_reg, G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_write_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, , , , );
G1_q_b[0] = G1_q_b[0]_PORT_B_data_out[0];


--A1L7 is altera_internal_jtag~TDO
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--A1L8 is altera_internal_jtag~TMSUTAP
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--A1L6 is altera_internal_jtag~TCKUTAP
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);


--N1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

N1_state[5] = AMPP_FUNCTION(!A1L6, N1_state[4], N1_state[3], A1L8, VCC);


--K1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

K1_Q[2] = AMPP_FUNCTION(!A1L6, K2_Q[2], K6_Q[2], K3_Q[0], !C1L2, C1L71);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(!A1L6, C1L22, C1_jtag_debug_mode, C1L32, N1_state[15], N1_state[0]);


--K4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

K4_Q[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1L2, C1L51);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L6, M1_dffs[0], M1_dffs[1], C1L72, C1L82, N1_state[0], N1_state[12]);


--K3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

K3_Q[0] = AMPP_FUNCTION(!A1L6, P1_dffe1a[1], !C1L2, C1L1);


--H1L01 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~26
--operation mode is normal

H1L01 = AMPP_FUNCTION(C1_jtag_debug_mode, K4_Q[0], C1_jtag_debug_mode_usr1, K3_Q[0]);


--H1L2 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

H1L2 = AMPP_FUNCTION(N1_state[5], K1_Q[2], H1L01);


--B1_Q1[0] is singt1:inst|Q1[0]
--operation mode is arithmetic

B1_Q1[0]_lut_out = !B1_Q1[0];
B1_Q1[0] = DFFEAS(B1_Q1[0]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );

--B1L31 is singt1:inst|Q1[0]~43
--operation mode is arithmetic

B1L31 = CARRY(B1_Q1[0]);


--B1_Q1[1] is singt1:inst|Q1[1]
--operation mode is arithmetic

B1_Q1[1]_carry_eqn = B1L31;
B1_Q1[1]_lut_out = B1_Q1[1] $ (B1_Q1[1]_carry_eqn);
B1_Q1[1] = DFFEAS(B1_Q1[1]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );

--B1L51 is singt1:inst|Q1[1]~47
--operation mode is arithmetic

B1L51 = CARRY(!B1L31 # !B1_Q1[1]);


--B1_Q1[2] is singt1:inst|Q1[2]
--operation mode is arithmetic

B1_Q1[2]_carry_eqn = B1L51;
B1_Q1[2]_lut_out = B1_Q1[2] $ (!B1_Q1[2]_carry_eqn);
B1_Q1[2] = DFFEAS(B1_Q1[2]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );

--B1L71 is singt1:inst|Q1[2]~51
--operation mode is arithmetic

B1L71 = CARRY(B1_Q1[2] & (!B1L51));


--B1_Q1[3] is singt1:inst|Q1[3]
--operation mode is arithmetic

B1_Q1[3]_carry_eqn = B1L71;
B1_Q1[3]_lut_out = B1_Q1[3] $ (B1_Q1[3]_carry_eqn);
B1_Q1[3] = DFFEAS(B1_Q1[3]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );

--B1L91 is singt1:inst|Q1[3]~55
--operation mode is arithmetic

B1L91 = CARRY(!B1L71 # !B1_Q1[3]);


--B1_Q1[4] is singt1:inst|Q1[4]
--operation mode is arithmetic

B1_Q1[4]_carry_eqn = B1L91;
B1_Q1[4]_lut_out = B1_Q1[4] $ (!B1_Q1[4]_carry_eqn);
B1_Q1[4] = DFFEAS(B1_Q1[4]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );

--B1L12 is singt1:inst|Q1[4]~59
--operation mode is arithmetic

B1L12 = CARRY(B1_Q1[4] & (!B1L91));


--B1_Q1[5] is singt1:inst|Q1[5]
--operation mode is normal

B1_Q1[5]_carry_eqn = B1L12;
B1_Q1[5]_lut_out = B1_Q1[5] $ (B1_Q1[5]_carry_eqn);
B1_Q1[5] = DFFEAS(B1_Q1[5]_lut_out, B1_CLK_CNT[4], VCC, , , , , , );


--H1_ram_rom_data_reg[7] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

H1_ram_rom_data_reg[7] = AMPP_FUNCTION(!A1L6, G1_q_b[7], H1L21, altera_internal_jtag, VCC, H1L63);


--H1_ram_rom_addr_reg[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]
--operation mode is arithmetic

H1_ram_rom_addr_reg[0] = AMPP_FUNCTION(!A1L6, H1_ram_rom_incr_addr, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], !K1_Q[0], H1L11);

--H1L71 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~85
--operation mode is arithmetic

H1L71 = AMPP_FUNCTION(H1_ram_rom_incr_addr, H1_ram_rom_addr_reg[0]);


--H1_ram_rom_addr_reg[1] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]
--operation mode is arithmetic

H1_ram_rom_addr_reg[1] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], !K1_Q[0], H1L11, H1L71);

--H1L91 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~89
--operation mode is arithmetic

H1L91 = AMPP_FUNCTION(H1_ram_rom_addr_reg[1], H1L71);


--H1_ram_rom_addr_reg[2] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]
--operation mode is arithmetic

H1_ram_rom_addr_reg[2] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], !K1_Q[0], H1L11, H1L91);

--H1L12 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~93
--operation mode is arithmetic

H1L12 = AMPP_FUNCTION(H1_ram_rom_addr_reg[2], H1L91);


--H1_ram_rom_addr_reg[3] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]
--operation mode is arithmetic

H1_ram_rom_addr_reg[3] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], !K1_Q[0], H1L11, H1L12);

--H1L32 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~97
--operation mode is arithmetic

H1L32 = AMPP_FUNCTION(H1_ram_rom_addr_reg[3], H1L12);


--H1_ram_rom_addr_reg[4] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]
--operation mode is arithmetic

H1_ram_rom_addr_reg[4] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5], !K1_Q[0], H1L11, H1L32);

--H1L52 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~101
--operation mode is arithmetic

H1L52 = AMPP_FUNCTION(H1_ram_rom_addr_reg[4], H1L32);


--H1_ram_rom_addr_reg[5] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]
--operation mode is normal

H1_ram_rom_addr_reg[5] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[5], A1L2, !K1_Q[0], H1L11, H1L52);


--H1_ram_rom_data_reg[6] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

H1_ram_rom_data_reg[6] = AMPP_FUNCTION(!A1L6, G1_q_b[6], H1_ram_rom_data_reg[7], H1L21, VCC, H1L63);


--H1_ram_rom_data_reg[5] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

H1_ram_rom_data_reg[5] = AMPP_FUNCTION(!A1L6, G1_q_b[5], H1_ram_rom_data_reg[6], H1L21, VCC, H1L63);


--H1_ram_rom_data_reg[4] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

H1_ram_rom_data_reg[4] = AMPP_FUNCTION(!A1L6, G1_q_b[4], H1_ram_rom_data_reg[5], H1L21, VCC, H1L63);


--H1_ram_rom_data_reg[3] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal