singt1.tan.qmsg

来自「采用vhdl语言编程」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[7\] singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0 12.848 ns memory " "Info: tco from clock \"clk\" to destination pin \"dout\[7\]\" through memory \"singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0\" is 12.848 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.973 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 350 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 350; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/实验3suc/Block1.bdf" { { 176 104 272 192 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0 2 MEM M4K_X17_Y14 8 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y14; Fanout = 8; MEM Node = 'singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_m372.tdf" "" { Text "D:/实验3suc/db/altsyncram_m372.tdf" 272 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 73.70 % ) " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk clk~out0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_m372.tdf" "" { Text "D:/实验3suc/db/altsyncram_m372.tdf" 272 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.225 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0 1 MEM M4K_X17_Y14 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y14; Fanout = 8; MEM Node = 'singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|ram_block3a7~porta_address_reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_m372.tdf" "" { Text "D:/实验3suc/db/altsyncram_m372.tdf" 272 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|q_a\[7\] 2 MEM M4K_X17_Y14 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y14; Fanout = 2; MEM Node = 'singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|altsyncram_m372:altsyncram1\|q_a\[7\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.308 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_a[7] } "NODE_NAME" } } { "db/altsyncram_m372.tdf" "" { Text "D:/实验3suc/db/altsyncram_m372.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.809 ns) + CELL(2.108 ns) 9.225 ns dout\[7\] 3 PIN PIN_225 0 " "Info: 3: + IC(2.809 ns) + CELL(2.108 ns) = 9.225 ns; Loc. = PIN_225; Fanout = 0; PIN Node = 'dout\[7\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.917 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_a[7] dout[7] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/实验3suc/Block1.bdf" { { 176 432 608 192 "dout\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns ( 69.55 % ) " "Info: Total cell delay = 6.416 ns ( 69.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.809 ns ( 30.45 % ) " "Info: Total interconnect delay = 2.809 ns ( 30.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.225 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_a[7] dout[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.225 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_a[7] dout[7] } { 0.000ns 0.000ns 2.809ns } { 0.000ns 4.308ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk clk~out0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.225 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg0 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_a[7] dout[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.225 ns" { singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~p