singt1.tan.qmsg

来自「采用vhdl语言编程」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\] register sld_hub:sld_hub_inst\|hub_tdo 119.3 MHz 8.382 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 119.3 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 8.382 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest register register " "Info: + Longest register to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\] 1 REG LC_X12_Y14_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y14_N1; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.590 ns) 1.147 ns sld_hub:sld_hub_inst\|hub_tdo~791 2 COMB LC_X12_Y14_N7 1 " "Info: 2: + IC(0.557 ns) + CELL(0.590 ns) = 1.147 ns; Loc. = LC_X12_Y14_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~791'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.147 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~791 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.590 ns) 2.170 ns sld_hub:sld_hub_inst\|hub_tdo~792 3 COMB LC_X12_Y14_N4 1 " "Info: 3: + IC(0.433 ns) + CELL(0.590 ns) = 2.170 ns; Loc. = LC_X12_Y14_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~792'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { sld_hub:sld_hub_inst|hub_tdo~791 sld_hub:sld_hub_inst|hub_tdo~792 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.478 ns) 3.900 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X13_Y12_N3 1 " "Info: 4: + IC(1.252 ns) + CELL(0.478 ns) = 3.900 ns; Loc. = LC_X13_Y12_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.730 ns" { sld_hub:sld_hub_inst|hub_tdo~792 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 42.51 % ) " "Info: Total cell delay = 1.658 ns ( 42.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.242 ns ( 57.49 % ) " "Info: Total interconnect delay = 2.242 ns ( 57.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~791 sld_hub:sld_hub_inst|hub_tdo~792 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~791 sld_hub:sld_hub_inst|hub_tdo~792 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.557ns 0.433ns 1.252ns } { 0.000ns 0.590ns 0.590ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.030 ns - Smallest " "Info: - Smallest clock skew is -0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.298 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 439 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 439; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.587 ns) + CELL(0.711 ns) 5.298 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X13_Y12_N3 1 " "Info: 2: + IC(4.587 ns) + CELL(0.711 ns) = 5.298 ns; Loc. = LC_X13_Y12_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.42 % ) " "Info: Total cell delay = 0.711 ns ( 13.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.587 ns ( 86.58 % ) " "Info: Total interconnect delay = 4.587 ns ( 86.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.587ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.328 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 439 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 439; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.617 ns) + CELL(0.711 ns) 5.328 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\] 2 REG LC_X12_Y14_N1 3 " "Info: 2: + IC(4.617 ns) + CELL(0.711 ns) = 5.328 ns; Loc. = LC_X12_Y14_N1; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.34 % ) " "Info: Total cell delay = 0.711 ns ( 13.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.617 ns ( 86.66 % ) " "Info: Total interconnect delay = 4.617 ns ( 86.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } { 0.000ns 4.617ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.587ns } { 0.000ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } { 0.000ns 4.617ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~791 sld_hub:sld_hub_inst|hub_tdo~792 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~791 sld_hub:sld_hub_inst|hub_tdo~792 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.557ns 0.433ns 1.252ns } { 0.000ns 0.590ns 0.590ns 0.478ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.298 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.587ns } { 0.000ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.328 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } { 0.000ns 4.617ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\] altera_internal_jtag altera_internal_jtag~TCKUTAP -0.728 ns register " "Info: tsu for register \"singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -0.728 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.533 ns + Longest pin register " "Info: + Longest pin to register delay is 4.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y10_N1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 13; PIN Node = 'altera_internal_jtag'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.883 ns) + CELL(0.442 ns) 2.325 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~953 2 COMB LC_X14_Y12_N5 3 " "Info: 2: + IC(1.883 ns) + CELL(0.442 ns) = 2.325 ns; Loc. = LC_X14_Y12_N5; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~953'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.601 ns) + CELL(0.607 ns) 4.533 ns singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\] 3 REG LC_X12_Y11_N1 1 " "Info: 3: + IC(1.601 ns) + CELL(0.607 ns) = 4.533 ns; Loc. = LC_X12_Y11_N1; Fanout = 1; REG Node = 'singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.208 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.049 ns ( 23.14 % ) " "Info: Total cell delay = 1.049 ns ( 23.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.484 ns ( 76.86 % ) " "Info: Total interconnect delay = 3.484 ns ( 76.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.533 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.533 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } { 0.000ns 1.883ns 1.601ns } { 0.000ns 0.442ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.298 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 439 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 439; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.587 ns) + CELL(0.711 ns) 5.298 ns singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\] 2 REG LC_X12_Y11_N1 1 " "Info: 2: + IC(4.587 ns) + CELL(0.711 ns) = 5.298 ns; Loc. = LC_X12_Y11_N1; Fanout = 1; REG Node = 'singt1:inst\|data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_fo51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:no_name_gen:info_rom_sr\|WORD_SR\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/61/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.42 % ) " "Info: Total cell delay = 0.711 ns ( 13.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.587 ns ( 86.58 % ) " "Info: Total interconnect delay = 4.587 ns ( 86.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.298 ns" { altera_internal_jtag~TCKUTAP singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } { 0.000ns 4.587ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.533 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.533 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~953 singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } { 0.000ns 1.883ns 1.601ns } { 0.000ns 0.442ns 0.607ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.298 ns" { altera_internal_jtag~TCKUTAP singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.298 ns" { altera_internal_jtag~TCKUTAP singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] } { 0.000ns 4.587ns } { 0.000ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}