singt1.tan.rpt

采用vhdl语言编程

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                              ; To                                                                                                                                                                                ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; -0.728 ns                        ; altera_internal_jtag                                                                                                                                                              ; singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 12.848 ns                        ; singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|ram_block3a7~porta_address_reg5                                ; dout[7]                                                                                                                                                                           ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                          ; altera_reserved_tdo                                                                                                                                                               ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.856 ns                         ; altera_internal_jtag                                                                                                                                                              ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                                                                                                        ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 119.30 MHz ( period = 8.382 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3]                                                                                                                                ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                      ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 140.75 MHz ( period = 7.105 ns ) ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_1fk:auto_generated|safe_q[3] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_lji2:auto_generated|ram_block1a4~porta_address_reg11                                    ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                   ;                                                                                                                                                                                   ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;