hdb3.txt

verilog 语言hdb 3 编 码 经过测试

//`timescale 1ns/1ns
module HDB3(nrz,ctx,rst,hdbp,hdbn);
input nrz,ctx,rst;
output hdbp,hdbn;
wire rst=0;
reg hdbp,hdbn;

reg[1:0] count0=2'b00;
reg[1:0] codeoutv;
wire clkb;
wire [0:0]nrz;
reg[4:0] s1;
reg[4:0] s0;
reg count1=1'b0;
reg firstv=1;
reg [0:0] flaglb=1'b0;

reg[1:0]codeoutb;
////////////////////////////////////////////////



////////////////////////////////////////////////



//assign clkb=~ctx;
always@(posedge ctx)
begin
//s0[0]=codeoutv[0];s1[0]=codeoutv[1];

//s0[3:0]<={s0[2:0],codeoutv[0]};
//s1[3:0]<={s1[2:0],codeoutv[1]};
 
//clkb=1;
if(rst==1)
begin
    codeoutv<=2'b00;
    count0<=2'b00;
end

else
begin
   case(nrz)
       1:
        begin   
          codeoutv<=2'b01;
          count0<=2'b00;
        end
       0:
       begin
           if(count0==2'b11)
              begin
               codeoutv<=2'b11;
               count0<=2'b00;
             end
          else 
             begin
                 count0<=count0+2'b01;
                 codeoutv<=2'b00;
             end
         end
       default:
          begin
              codeoutv<=2'b00;
              count0<=count0;
          end
endcase

s0[3:0]<={s0[2:0],codeoutv[0]};
s1[3:0]<={s1[2:0],codeoutv[1]};
end
end
//assign s0[0]=codeoutv[0];s1[0]=codeoutv[1];
//clkb=~ctx;




//always@(posedge clkb)
always@(posedge ctx)
begin
//s0[3:0]<={s0[2:0],codeoutv[0]};
//s1[3:0]<={s1[2:0],codeoutv[1]};
    
   codeoutb<={s1[4],s0[4]}; 
    case(codeoutv)//???v?
    2'b11:
      begin
         case(firstv)//v??v?
            0:
                begin
                 count1<=0;
                 firstv<=1;
                 s1[4]<=s1[3];
                 s0[4]<=s0[3];
                end
            1: //when firstv==1
               begin
                  if(count1==0)
                   begin
              //  s1[4]<=1;
               // s0[4]<=0;
                  s1[3]<=1;
                  s0[3]<=0; 
                  s1[4]<=s1[3];
                  s0[4]<=s0[3];
                   count1<=0;
                   end
               else//when count1==1
                begin
                 s1[4]<=s1[3];
                 s0[4]<=s0[3];
                 count1<=0;
                end
            end
    endcase
    end
 
    2'b01://???1?
    begin
        count1<=count1+1;
        s1[4]<=s1[3];
        s0[4]<=s0[3];
    end
    default://codeoutv?????
      begin
        count1<=count1;
        s1[4]<=s1[3];
        s0[4]<=s0[3];
       end
 endcase 
 
 
 
  
 end  
// assign codeoutb<={s1[4],s0[4]};
 
 
 always@(posedge ctx)
 
 begin
    case(codeoutb)
    2'b01:
       begin
          if(flaglb==1'b1)
             begin
                hdbp<=1;
                hdbn<=0;
                flaglb<=1'b0;
            end
        else
           begin
              hdbp<=0;
              hdbn<=1;
            flaglb<=1'b1;
          end
    end
    
    2'b10:
    begin
          if(flaglb==1'b1)
             begin
                hdbp<=1;
                hdbn<=0;
                 flaglb<=1'b0;
            end
        else
           begin
              hdbp<=0;
              hdbn<=1;
               flaglb<=1'b1;
          end
    end
    
    
    2'b11:
       
     //  if(codeoutb==2'b11)
       begin
          if(flaglb==1'b1)
             begin
             hdbp<=0;
             hdbn<=1;
            end
        else
              begin
              hdbp<=1;
              hdbn<=0;
             end
   end      
    default:
          begin
              hdbp<=0;
              hdbn<=0;
              flaglb<=flaglb;
             end     
        
   endcase 
end
endmodule