timer.v

来自「数字钟设计」· Verilog 代码 · 共 84 行

module timer(
               alarm_out,  //outputs
               hour_timer_1,
               hour_timer_2,
               minute_timer_1,
               minute_timer_2,
               hour_led_1, //inputs
               hour_led_2,
               minute_led_1,
               minute_led_2,  
               alarm_switch,
               clk,
               reset_b,
               hour_led_11, //temp_time inputs
               hour_led_22,
               minute_led_11,
               minute_led_22,
               setup_enable,
               sel,
               pm_am_in,
               pm_am_in_1);
output         alarm_out;
output   [6:0] hour_timer_1;
output   [6:0] hour_timer_2;
output   [6:0] minute_timer_1;
output   [6:0] minute_timer_2;

input           setup_enable;
input           sel;
input     [6:0] hour_led_1;
input     [6:0] hour_led_2;
input     [6:0] minute_led_1;
input     [6:0] minute_led_2;
input           alarm_switch;
input           clk;
input           reset_b;
input     [6:0] hour_led_11; //temp_time inputs
input     [6:0] hour_led_22;
input     [6:0] minute_led_11;
input     [6:0] minute_led_22;

input           pm_am_in;  //timer
input           pm_am_in_1;//counter
                                     
reg        [6:0] hour_timer_1;
reg        [6:0] hour_timer_2;
reg        [6:0] minute_timer_1;
reg        [6:0] minute_timer_2;

reg              alarm_out;

always@(posedge clk or negedge reset_b)
 begin
  if(!reset_b)
   alarm_out<=0;
  else
if(alarm_switch==1&&minute_timer_2==minute_led_2&&minute_timer_1==minute_led_1&&hour_timer_2==hour_led_2
&&hour_timer_1==hour_led_1&&pm_am_in==pm_am_in_1)
         alarm_out<=1;
  else
   alarm_out<=0;
 end
  
always@(posedge clk or negedge reset_b)
 begin
  if(!reset_b)
   begin
    hour_timer_1<=0;
    hour_timer_2<=0;
    minute_timer_1<=0;
    minute_timer_2<=0;
   end
  else
   if(setup_enable==1&&sel==1)
    begin
     hour_timer_1<=hour_led_11;
     hour_timer_2<=hour_led_22;
     minute_timer_1<=minute_led_11;
     minute_timer_2<=minute_led_22;
    end               
 end
endmodule