temp_time.v

来自「数字钟设计」· Verilog 代码 · 共 137 行

module temp_time(
               hour_led_11, //outputs
               hour_led_22,
               minute_led_11,
               minute_led_22,  
               pm_am_led,  
               clk,    //inputs
               reset_b,
               minute_in,
               hour_in,
               pm_am_in);

output     [6:0] hour_led_11;
output     [6:0] hour_led_22;
output     [6:0] minute_led_11;
output     [6:0] minute_led_22;
output           pm_am_led;
input            clk;
input            reset_b;
input      [5:0] minute_in;
input      [3:0] hour_in;
input            pm_am_in;
                               
reg        [6:0] hour_led_11;
reg        [6:0] hour_led_22;
reg        [6:0] minute_led_11;
reg        [6:0] minute_led_22;
reg        [6:0] hour_temp_1;
reg        [6:0] hour_temp_2;
reg        [6:0] minute_temp_1;
reg        [6:0] minute_temp_2;
reg        [5:0] minute_temp_in;
reg        [3:0] hour_temp_in;
reg              pm_am_led;

always@(posedge clk or negedge reset_b)
 begin
  if(!reset_b)
   begin
    hour_temp_1<=0;
    hour_temp_2<=0;
    minute_temp_1<=0;
    minute_temp_2<=0;
    minute_temp_in<=0;
    hour_temp_in<=0;
    hour_led_11<=0;
    hour_led_22<=0;
    minute_led_11<=0;
    minute_led_22<=0;
    pm_am_led<=0;
   end
  else
      begin   
       minute_temp_in<=minute_in;
       hour_temp_in<=hour_in;
       pm_am_led<=pm_am_in;
        if(minute_temp_in<60)
         begin
         if(minute_temp_in<50)
          if(minute_temp_in<40)
           if(minute_temp_in<30)
            if(minute_temp_in<20)
             if(minute_temp_in<10)
              begin
               minute_led_22<=minute_temp_in;
               minute_led_11<=0;
              end
             else
              begin
               minute_led_22<=minute_temp_in-10;
               minute_led_11<=1;
              end
            else
             begin
              minute_led_22<=minute_temp_in-20;
              minute_led_11<=2;
             end
           else
            begin
             minute_led_22<=minute_temp_in-30;
             minute_led_11<=3;
            end
          else
           begin
             minute_led_22<=minute_temp_in-40;
             minute_led_11<=4;
           end
         else
          begin
             minute_led_22<=minute_temp_in-50;
             minute_led_11<=5;
           end
         end
      
        if(hour_temp_in<60)
         begin
         if(hour_temp_in<50)
          if(hour_temp_in<40)
           if(hour_temp_in<30)
            if(hour_temp_in<20)
             if(hour_temp_in<10)
              begin
               hour_led_22<=hour_temp_in;
               hour_led_11<=0;
              end
             else
              begin
               hour_led_22<=hour_temp_in-10;
               hour_led_11<=1;
              end
            else
             begin
              hour_led_22<=hour_temp_in-20;
              hour_led_11<=2;
             end
           else
            begin
             hour_led_22<=hour_temp_in-30;
             hour_led_11<=3;
            end
          else
           begin
             hour_led_22<=hour_temp_in-40;
             hour_led_11<=4;
           end
         else
          begin
             hour_led_22<=hour_temp_in-50;
             hour_led_11<=5;
           end
         end
       
      end
 end
endmodule