onebitincrement.vhd

来自「用VHDL编译的源代码」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
entity onebitincrement is
   port(
      i,cin: in std_logic;
      cout,s: out std_logic
   );
end onebitincrement;

architecture one of onebitincrement is
begin
   s<=NOT (i XOR (NOT cin));
   cout<=i AND cin;
end one;