lab7.tan.summary

来自「用VHDL编译的源代码」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.927 ns
From           : heartbeat:u1|d0_reg[0]
To             : ssega[1]
From Clock     : clk1
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 175.19 MHz ( period = 5.708 ns )
From           : heartbeat:u1|ms_reg[20]
To             : heartbeat:u1|d0_reg[2]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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