heartbeat.vhd

用VHDL编译的源代码

llibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity heartbeat is
port(
     clk:in std_logic;
     d0,d1,d2,d3:out std_logic_vector(3 downto 0)
);
end heartbeat;

architecture one of heartbeat is
constant numb:integer:=4;
signal ms_reg, ms_next: unsigned(2 downto 0);
signal d3_reg,d2_reg, d1_reg, d0_reg:unsigned(3 downto 0);
signal d3_next,d2_next, d1_next, d0_next:unsigned(3 downto 0);
signal d3_en,d1_en, d2_en, d0_en:std_logic;
signal ms_tick: std_logic;


 begin
  process(clk)
  begin 
     if(clk'event and clk='1') then
        ms_reg<=ms_next;
        d3_reg<=d3_next;        
        d2_reg<=d2_next;
        d1_reg<=d1_next;
        d0_reg<=d0_next;
     end if;
  end process;
  
  ms_next<=
        (others=>'0') when ms_reg=numb else
        ms_reg+1; 
  ms_tick<='1' when ms_reg=numb else '0';
  

---- counter

  d1_en<='1' when ms_tick='1' else '0';
  d1_next<=
         "0000" when d1_en='1' and d1_reg=3 else
         d1_reg+1  when d1_en='1' else
         d1_reg;
         
         
---- counter
  d0_en<='1' when ms_tick='1' else '0';
  d0_next<=
         "0000" when d0_en='1' and d0_reg=3 else
         d0_reg+1 when d0_en='1' else
         d0_reg;



---- counter
  d2_en<='1' when ms_tick='1' else '0';
  d2_next<=
         "0000" when d2_en='1' and d2_reg=3 else
         d2_reg+1 when d2_en='1' else
         d2_reg;

---- counter
  d3_en<='1' when ms_tick='1' else '0';
  d3_next<=
         "0000" when d3_en='1' and d3_reg=3 else
         d3_reg+1 when d3_en='1' else
         d3_reg;

 
  d0<=std_logic_vector(d0_reg);
  d1<=std_logic_vector(d1_reg);
  d2<=std_logic_vector(d2_reg);
  d3<=std_logic_vector(d3_reg); 
end one;