lab7.qsf

用VHDL编译的源代码

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		lab7_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY lab7
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:49:44  OCTOBER 21, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION "8.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VHDL_FILE lab7.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE lab7.vwf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_L1 -to clk1
set_location_assignment PIN_J2 -to ssega[0]
set_location_assignment PIN_J1 -to ssega[1]
set_location_assignment PIN_H2 -to ssega[2]
set_location_assignment PIN_H1 -to ssega[3]
set_location_assignment PIN_F2 -to ssega[4]
set_location_assignment PIN_F1 -to ssega[5]
set_location_assignment PIN_E2 -to ssega[6]
set_location_assignment PIN_E1 -to ssegb[0]
set_location_assignment PIN_H6 -to ssegb[1]
set_location_assignment PIN_H5 -to ssegb[2]
set_location_assignment PIN_H4 -to ssegb[3]
set_location_assignment PIN_G3 -to ssegb[4]
set_location_assignment PIN_D2 -to ssegb[5]
set_location_assignment PIN_D1 -to ssegb[6]
set_location_assignment PIN_G5 -to ssegc[0]
set_location_assignment PIN_G6 -to ssegc[1]
set_location_assignment PIN_C2 -to ssegc[2]
set_location_assignment PIN_C1 -to ssegc[3]
set_location_assignment PIN_E3 -to ssegc[4]
set_location_assignment PIN_E4 -to ssegc[5]
set_location_assignment PIN_D3 -to ssegc[6]
set_location_assignment PIN_F4 -to ssegd[0]
set_location_assignment PIN_D5 -to ssegd[1]
set_location_assignment PIN_D6 -to ssegd[2]
set_location_assignment PIN_J4 -to ssegd[3]
set_location_assignment PIN_L8 -to ssegd[4]
set_location_assignment PIN_F3 -to ssegd[5]
set_location_assignment PIN_D4 -to ssegd[6]
set_global_assignment -name USE_CONFIGURATION_DEVICE ON