ppg.vhd.bak

用VHDL编译的源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ppg is
port(
   clk,reset:in std_logic;
   w,d:in std_logic_vector(3 downto 0);
   pwm_pulse:out std_logic
   );
end ppg;

architecture two_seg_arch of ppg is
signal r_reg:unsigned(4 downto 0);
signal r_next:unsigned(4 downto 0);  
signal buf_reg:std_logic;
signal buf_next:std_logic;
begin
process(clk,reset)
begin
  if (reset='1') then
    r_reg<=(others=>'0');
    buf_reg<='0';
  elsif (clk'event and clk='1') then
    r_reg<=r_next;
    buf_reg<=buf_next;
  end if;
end process;

r_next<=
"00000" when (to_integer(r_reg)=to_integer(unsigned(d))+to_integer(unsigned(w))) else
r_reg+1;
 
 
buf_next<=
'1' when (to_integer(r_reg)<to_integer(unsigned(d))) else
'0' when (to_integer(r_reg)>to_integer(unsigned(d))) and (to_integer(r_reg)<to_integer(unsigned(d)+to_integer(unsigned(w)));
pwm_pulse<=buf_reg;
end two_seg_arch;