lab5.tan.summary

秒表可计时

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.552 ns
From           : up1
To             : lab5stopwatch:u1|d3_reg[0]
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.167 ns
From           : lab5stopwatch:u1|d3_reg[2]
To             : sseg4[1]
From Clock     : clk1
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.470 ns
From           : clr1
To             : lab5stopwatch:u1|d0_reg[3]
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 120.48 MHz ( period = 8.300 ns )
From           : lab5stopwatch:u1|d2_reg[2]
To             : lab5stopwatch:u1|d3_reg[0]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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