lab5.map.rpt

秒表可计时

; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                         ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                            ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------+
; lab5.vhd                         ; yes             ; User VHDL File  ; G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd          ;
; lab5stopwatch.vhd                ; yes             ; User VHDL File  ; G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd ;
; bin2led.vhd                      ; yes             ; Other           ; G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/bin2led.vhd       ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 129   ;
;                                             ;       ;
; Total combinational functions               ; 129   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 80    ;
;     -- 3 input functions                    ; 17    ;
;     -- <=2 input functions                  ; 32    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 104   ;
;     -- arithmetic mode                      ; 25    ;
;                                             ;       ;
; Total registers                             ; 39    ;
;     -- Dedicated logic registers            ; 39    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 32    ;
; Maximum fan-out node                        ; clk1  ;
; Maximum fan-out                             ; 39    ;
; Total fan-out                               ; 563   ;
; Average fan-out                             ; 2.81  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name    ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; |lab5                      ; 129 (0)           ; 39 (0)       ; 0           ; 0            ; 0       ; 0         ; 32   ; 0            ; |lab5                  ; work         ;
;    |bin2led:u2|            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bin2led:u2       ; work         ;
;    |bin2led:u3|            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bin2led:u3       ; work         ;
;    |bin2led:u4|            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bin2led:u4       ; work         ;
;    |bin2led:u5|            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bin2led:u5       ; work         ;
;    |lab5stopwatch:u1|      ; 101 (101)         ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|lab5stopwatch:u1 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 39    ;
; Number of registers using Synchronous Clear  ; 23    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |lab5|lab5stopwatch:u1|d3_reg[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Oct 14 14:40:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5
Info: Found 2 design units, including 1 entities, in source file lab5.vhd
    Info: Found design unit 1: lab5-one
    Info: Found entity 1: lab5
Info: Found 2 design units, including 1 entities, in source file lab5stopwatch.vhd
    Info: Found design unit 1: lab5stopwatch-cascade_arch
    Info: Found entity 1: lab5stopwatch
Info: Elaborating entity "lab5" for the top level hierarchy
Info: Elaborating entity "lab5stopwatch" for hierarchy "lab5stopwatch:u1"
Warning: Using design file bin2led.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bin2led-arch
    Info: Found entity 1: bin2led
Info: Elaborating entity "bin2led" for hierarchy "bin2led:u2"
Info: Implemented 161 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 28 output pins
    Info: Implemented 129 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 182 megabytes
    Info: Processing ended: Tue Oct 14 14:40:34 2008
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:04