lab5.hier_info

秒表可计时

|lab5
up1 => lab5stopwatch:u1.up
clk1 => lab5stopwatch:u1.clk
go1 => lab5stopwatch:u1.go
clr1 => lab5stopwatch:u1.clr
sseg1[0] <= bin2led:u2.sseg[0]
sseg1[1] <= bin2led:u2.sseg[1]
sseg1[2] <= bin2led:u2.sseg[2]
sseg1[3] <= bin2led:u2.sseg[3]
sseg1[4] <= bin2led:u2.sseg[4]
sseg1[5] <= bin2led:u2.sseg[5]
sseg1[6] <= bin2led:u2.sseg[6]
sseg2[0] <= bin2led:u3.sseg[0]
sseg2[1] <= bin2led:u3.sseg[1]
sseg2[2] <= bin2led:u3.sseg[2]
sseg2[3] <= bin2led:u3.sseg[3]
sseg2[4] <= bin2led:u3.sseg[4]
sseg2[5] <= bin2led:u3.sseg[5]
sseg2[6] <= bin2led:u3.sseg[6]
sseg3[0] <= bin2led:u4.sseg[0]
sseg3[1] <= bin2led:u4.sseg[1]
sseg3[2] <= bin2led:u4.sseg[2]
sseg3[3] <= bin2led:u4.sseg[3]
sseg3[4] <= bin2led:u4.sseg[4]
sseg3[5] <= bin2led:u4.sseg[5]
sseg3[6] <= bin2led:u4.sseg[6]
sseg4[0] <= bin2led:u5.sseg[0]
sseg4[1] <= bin2led:u5.sseg[1]
sseg4[2] <= bin2led:u5.sseg[2]
sseg4[3] <= bin2led:u5.sseg[3]
sseg4[4] <= bin2led:u5.sseg[4]
sseg4[5] <= bin2led:u5.sseg[5]
sseg4[6] <= bin2led:u5.sseg[6]


|lab5|lab5stopwatch:u1
up => d3_next~18.IN0
up => d3_next~5.IN0
up => d2_next~18.IN0
up => d2_next~5.IN0
up => d1_next~18.IN0
up => d1_next~5.IN0
up => d0_next~5.IN1
up => d0_next~0.IN1
up => d1_next~11.IN0
up => d1_next~0.IN0
up => d2_next~11.IN0
up => d2_next~0.IN0
up => d3_next~11.IN0
up => d3_next~0.IN0
clk => ms_reg[22].CLK
clk => ms_reg[21].CLK
clk => ms_reg[20].CLK
clk => ms_reg[19].CLK
clk => ms_reg[18].CLK
clk => ms_reg[17].CLK
clk => ms_reg[16].CLK
clk => ms_reg[15].CLK
clk => ms_reg[14].CLK
clk => ms_reg[13].CLK
clk => ms_reg[12].CLK
clk => ms_reg[11].CLK
clk => ms_reg[10].CLK
clk => ms_reg[9].CLK
clk => ms_reg[8].CLK
clk => ms_reg[7].CLK
clk => ms_reg[6].CLK
clk => ms_reg[5].CLK
clk => ms_reg[4].CLK
clk => ms_reg[3].CLK
clk => ms_reg[2].CLK
clk => ms_reg[1].CLK
clk => ms_reg[0].CLK
clk => d3_reg[3].CLK
clk => d3_reg[2].CLK
clk => d3_reg[1].CLK
clk => d3_reg[0].CLK
clk => d2_reg[3].CLK
clk => d2_reg[2].CLK
clk => d2_reg[1].CLK
clk => d2_reg[0].CLK
clk => d1_reg[3].CLK
clk => d1_reg[2].CLK
clk => d1_reg[1].CLK
clk => d1_reg[0].CLK
clk => d0_reg[3].CLK
clk => d0_reg[2].CLK
clk => d0_reg[1].CLK
clk => d0_reg[0].CLK
go => ms_next~23.IN0
go => ms_next~22.OUTPUTSELECT
go => ms_next~21.OUTPUTSELECT
go => ms_next~20.OUTPUTSELECT
go => ms_next~19.OUTPUTSELECT
go => ms_next~18.OUTPUTSELECT
go => ms_next~17.OUTPUTSELECT
go => ms_next~16.OUTPUTSELECT
go => ms_next~15.OUTPUTSELECT
go => ms_next~14.OUTPUTSELECT
go => ms_next~13.OUTPUTSELECT
go => ms_next~12.OUTPUTSELECT
go => ms_next~11.OUTPUTSELECT
go => ms_next~10.OUTPUTSELECT
go => ms_next~9.OUTPUTSELECT
go => ms_next~8.OUTPUTSELECT
go => ms_next~7.OUTPUTSELECT
go => ms_next~6.OUTPUTSELECT
go => ms_next~5.OUTPUTSELECT
go => ms_next~4.OUTPUTSELECT
go => ms_next~3.OUTPUTSELECT
go => ms_next~2.OUTPUTSELECT
go => ms_next~1.OUTPUTSELECT
go => ms_next~0.OUTPUTSELECT
clr => d3_next~19.IN0
clr => d3_next~12.IN0
clr => d2_next~19.IN0
clr => d2_next~12.IN0
clr => d1_next~19.IN0
clr => d1_next~12.IN0
clr => d0_next~15.IN0
clr => d0_next~10.IN0
clr => ms_next~24.IN1
d3[0] <= d3_reg[0].DB_MAX_OUTPUT_PORT_TYPE
d3[1] <= d3_reg[1].DB_MAX_OUTPUT_PORT_TYPE
d3[2] <= d3_reg[2].DB_MAX_OUTPUT_PORT_TYPE
d3[3] <= d3_reg[3].DB_MAX_OUTPUT_PORT_TYPE
d2[0] <= d2_reg[0].DB_MAX_OUTPUT_PORT_TYPE
d2[1] <= d2_reg[1].DB_MAX_OUTPUT_PORT_TYPE
d2[2] <= d2_reg[2].DB_MAX_OUTPUT_PORT_TYPE
d2[3] <= d2_reg[3].DB_MAX_OUTPUT_PORT_TYPE
d1[0] <= d1_reg[0].DB_MAX_OUTPUT_PORT_TYPE
d1[1] <= d1_reg[1].DB_MAX_OUTPUT_PORT_TYPE
d1[2] <= d1_reg[2].DB_MAX_OUTPUT_PORT_TYPE
d1[3] <= d1_reg[3].DB_MAX_OUTPUT_PORT_TYPE
d0[0] <= d0_reg[0].DB_MAX_OUTPUT_PORT_TYPE
d0[1] <= d0_reg[1].DB_MAX_OUTPUT_PORT_TYPE
d0[2] <= d0_reg[2].DB_MAX_OUTPUT_PORT_TYPE
d0[3] <= d0_reg[3].DB_MAX_OUTPUT_PORT_TYPE


|lab5|bin2led:u2
bin[0] => Mux6.IN19
bin[0] => Mux5.IN19
bin[0] => Mux4.IN19
bin[0] => Mux3.IN19
bin[0] => Mux2.IN19
bin[0] => Mux1.IN19
bin[0] => Mux0.IN19
bin[1] => Mux6.IN18
bin[1] => Mux5.IN18
bin[1] => Mux4.IN18
bin[1] => Mux3.IN18
bin[1] => Mux2.IN18
bin[1] => Mux1.IN18
bin[1] => Mux0.IN18
bin[2] => Mux6.IN17
bin[2] => Mux5.IN17
bin[2] => Mux4.IN17
bin[2] => Mux3.IN17
bin[2] => Mux2.IN17
bin[2] => Mux1.IN17
bin[2] => Mux0.IN17
bin[3] => Mux6.IN16
bin[3] => Mux5.IN16
bin[3] => Mux4.IN16
bin[3] => Mux3.IN16
bin[3] => Mux2.IN16
bin[3] => Mux1.IN16
bin[3] => Mux0.IN16
sseg[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
sseg[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
sseg[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
sseg[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
sseg[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
sseg[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
sseg[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|lab5|bin2led:u3
bin[0] => Mux6.IN19
bin[0] => Mux5.IN19
bin[0] => Mux4.IN19
bin[0] => Mux3.IN19
bin[0] => Mux2.IN19
bin[0] => Mux1.IN19
bin[0] => Mux0.IN19
bin[1] => Mux6.IN18
bin[1] => Mux5.IN18
bin[1] => Mux4.IN18
bin[1] => Mux3.IN18
bin[1] => Mux2.IN18
bin[1] => Mux1.IN18
bin[1] => Mux0.IN18
bin[2] => Mux6.IN17
bin[2] => Mux5.IN17
bin[2] => Mux4.IN17
bin[2] => Mux3.IN17
bin[2] => Mux2.IN17
bin[2] => Mux1.IN17
bin[2] => Mux0.IN17
bin[3] => Mux6.IN16
bin[3] => Mux5.IN16
bin[3] => Mux4.IN16
bin[3] => Mux3.IN16
bin[3] => Mux2.IN16
bin[3] => Mux1.IN16
bin[3] => Mux0.IN16
sseg[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
sseg[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
sseg[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
sseg[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
sseg[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
sseg[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
sseg[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|lab5|bin2led:u4
bin[0] => Mux6.IN19
bin[0] => Mux5.IN19
bin[0] => Mux4.IN19
bin[0] => Mux3.IN19
bin[0] => Mux2.IN19
bin[0] => Mux1.IN19
bin[0] => Mux0.IN19
bin[1] => Mux6.IN18
bin[1] => Mux5.IN18
bin[1] => Mux4.IN18
bin[1] => Mux3.IN18
bin[1] => Mux2.IN18
bin[1] => Mux1.IN18
bin[1] => Mux0.IN18
bin[2] => Mux6.IN17
bin[2] => Mux5.IN17
bin[2] => Mux4.IN17
bin[2] => Mux3.IN17
bin[2] => Mux2.IN17
bin[2] => Mux1.IN17
bin[2] => Mux0.IN17
bin[3] => Mux6.IN16
bin[3] => Mux5.IN16
bin[3] => Mux4.IN16
bin[3] => Mux3.IN16
bin[3] => Mux2.IN16
bin[3] => Mux1.IN16
bin[3] => Mux0.IN16
sseg[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
sseg[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
sseg[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
sseg[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
sseg[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
sseg[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
sseg[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|lab5|bin2led:u5
bin[0] => Mux6.IN19
bin[0] => Mux5.IN19
bin[0] => Mux4.IN19
bin[0] => Mux3.IN19
bin[0] => Mux2.IN19
bin[0] => Mux1.IN19
bin[0] => Mux0.IN19
bin[1] => Mux6.IN18
bin[1] => Mux5.IN18
bin[1] => Mux4.IN18
bin[1] => Mux3.IN18
bin[1] => Mux2.IN18
bin[1] => Mux1.IN18
bin[1] => Mux0.IN18
bin[2] => Mux6.IN17
bin[2] => Mux5.IN17
bin[2] => Mux4.IN17
bin[2] => Mux3.IN17
bin[2] => Mux2.IN17
bin[2] => Mux1.IN17
bin[2] => Mux0.IN17
bin[3] => Mux6.IN16
bin[3] => Mux5.IN16
bin[3] => Mux4.IN16
bin[3] => Mux3.IN16
bin[3] => Mux2.IN16
bin[3] => Mux1.IN16
bin[3] => Mux0.IN16
sseg[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
sseg[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
sseg[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
sseg[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
sseg[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
sseg[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
sseg[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE