prev_cmp_lab5.qmsg

秒表可计时

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lab5 -c lab5 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lab5 -c lab5" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Peak virtual memory: 177 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 14 14:40:55 2008 " "Info: Processing ended: Tue Oct 14 14:40:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 14 14:40:56 2008 " "Info: Processing started: Tue Oct 14 14:40:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lab5 -c lab5 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab5 -c lab5 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } } { "c:/eda/altera/v80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/eda/altera/v80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register lab5stopwatch:u1\|d2_reg\[2\] register lab5stopwatch:u1\|d3_reg\[0\] 120.48 MHz 8.3 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 120.48 MHz between source register \"lab5stopwatch:u1\|d2_reg\[2\]\" and destination register \"lab5stopwatch:u1\|d3_reg\[0\]\" (period= 8.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.065 ns + Longest register register " "Info: + Longest register to register delay is 8.065 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lab5stopwatch:u1\|d2_reg\[2\] 1 REG LCFF_X15_Y16_N29 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y16_N29; Fanout = 12; REG Node = 'lab5stopwatch:u1\|d2_reg\[2\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lab5stopwatch:u1|d2_reg[2] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.209 ns) + CELL(0.507 ns) 2.716 ns lab5stopwatch:u1\|Equal5~30 2 COMB LCCOMB_X1_Y24_N30 2 " "Info: 2: + IC(2.209 ns) + CELL(0.507 ns) = 2.716 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 2; COMB Node = 'lab5stopwatch:u1\|Equal5~30'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.716 ns" { lab5stopwatch:u1|d2_reg[2] lab5stopwatch:u1|Equal5~30 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.192 ns) + CELL(0.178 ns) 5.086 ns lab5stopwatch:u1\|d2_next~1381 3 COMB LCCOMB_X29_Y16_N0 8 " "Info: 3: + IC(2.192 ns) + CELL(0.178 ns) = 5.086 ns; Loc. = LCCOMB_X29_Y16_N0; Fanout = 8; COMB Node = 'lab5stopwatch:u1\|d2_next~1381'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { lab5stopwatch:u1|Equal5~30 lab5stopwatch:u1|d2_next~1381 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.178 ns) 5.589 ns lab5stopwatch:u1\|d3_reg\[1\]~295 4 COMB LCCOMB_X29_Y16_N20 4 " "Info: 4: + IC(0.325 ns) + CELL(0.178 ns) = 5.589 ns; Loc. = LCCOMB_X29_Y16_N20; Fanout = 4; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~295'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.178 ns) 6.653 ns lab5stopwatch:u1\|d3_reg\[1\]~296 5 COMB LCCOMB_X29_Y15_N26 1 " "Info: 5: + IC(0.886 ns) + CELL(0.178 ns) = 6.653 ns; Loc. = LCCOMB_X29_Y15_N26; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~296'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.178 ns) 7.969 ns lab5stopwatch:u1\|d3_reg\[0\]~297 6 COMB LCCOMB_X27_Y16_N4 1 " "Info: 6: + IC(1.138 ns) + CELL(0.178 ns) = 7.969 ns; Loc. = LCCOMB_X27_Y16_N4; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[0\]~297'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 8.065 ns lab5stopwatch:u1\|d3_reg\[0\] 7 REG LCFF_X27_Y16_N5 11 " "Info: 7: + IC(0.000 ns) + CELL(0.096 ns) = 8.065 ns; Loc. = LCFF_X27_Y16_N5; Fanout = 11; REG Node = 'lab5stopwatch:u1\|d3_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.315 ns ( 16.31 % ) " "Info: Total cell delay = 1.315 ns ( 16.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.750 ns ( 83.69 % ) " "Info: Total interconnect delay = 6.750 ns ( 83.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "8.065 ns" { lab5stopwatch:u1|d2_reg[2] lab5stopwatch:u1|Equal5~30 lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "8.065 ns" { lab5stopwatch:u1|d2_reg[2] {} lab5stopwatch:u1|Equal5~30 {} lab5stopwatch:u1|d2_next~1381 {} lab5stopwatch:u1|d3_reg[1]~295 {} lab5stopwatch:u1|d3_reg[1]~296 {} lab5stopwatch:u1|d3_reg[0]~297 {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 2.209ns 2.192ns 0.325ns 0.886ns 1.138ns 0.000ns } { 0.000ns 0.507ns 0.178ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.853 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 39 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 39; COMB Node = 'clk1~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns lab5stopwatch:u1\|d3_reg\[0\] 3 REG LCFF_X27_Y16_N5 11 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X27_Y16_N5; Fanout = 11; REG Node = 'lab5stopwatch:u1\|d3_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.849 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 39 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 39; COMB Node = 'clk1~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.602 ns) 2.849 ns lab5stopwatch:u1\|d2_reg\[2\] 3 REG LCFF_X15_Y16_N29 12 " "Info: 3: + IC(0.983 ns) + CELL(0.602 ns) = 2.849 ns; Loc. = LCFF_X15_Y16_N29; Fanout = 12; REG Node = 'lab5stopwatch:u1\|d2_reg\[2\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { clk1~clkctrl lab5stopwatch:u1|d2_reg[2] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.14 % ) " "Info: Total cell delay = 1.628 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.221 ns ( 42.86 % ) " "Info: Total interconnect delay = 1.221 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.849 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d2_reg[2] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.849 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d2_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.983ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.849 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d2_reg[2] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.849 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d2_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.983ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "8.065 ns" { lab5stopwatch:u1|d2_reg[2] lab5stopwatch:u1|Equal5~30 lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "8.065 ns" { lab5stopwatch:u1|d2_reg[2] {} lab5stopwatch:u1|Equal5~30 {} lab5stopwatch:u1|d2_next~1381 {} lab5stopwatch:u1|d3_reg[1]~295 {} lab5stopwatch:u1|d3_reg[1]~296 {} lab5stopwatch:u1|d3_reg[0]~297 {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 2.209ns 2.192ns 0.325ns 0.886ns 1.138ns 0.000ns } { 0.000ns 0.507ns 0.178ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.849 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d2_reg[2] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.849 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d2_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.983ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lab5stopwatch:u1\|d3_reg\[0\] up1 clk1 3.552 ns register " "Info: tsu for register \"lab5stopwatch:u1\|d3_reg\[0\]\" (data pin = \"up1\", clock pin = \"clk1\") is 3.552 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.443 ns + Longest pin register " "Info: + Longest pin to register delay is 6.443 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns up1 1 PIN PIN_M22 17 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 17; PIN Node = 'up1'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { up1 } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.485 ns) 3.464 ns lab5stopwatch:u1\|d2_next~1381 2 COMB LCCOMB_X29_Y16_N0 8 " "Info: 2: + IC(1.943 ns) + CELL(0.485 ns) = 3.464 ns; Loc. = LCCOMB_X29_Y16_N0; Fanout = 8; COMB Node = 'lab5stopwatch:u1\|d2_next~1381'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.428 ns" { up1 lab5stopwatch:u1|d2_next~1381 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.178 ns) 3.967 ns lab5stopwatch:u1\|d3_reg\[1\]~295 3 COMB LCCOMB_X29_Y16_N20 4 " "Info: 3: + IC(0.325 ns) + CELL(0.178 ns) = 3.967 ns; Loc. = LCCOMB_X29_Y16_N20; Fanout = 4; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~295'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.178 ns) 5.031 ns lab5stopwatch:u1\|d3_reg\[1\]~296 4 COMB LCCOMB_X29_Y15_N26 1 " "Info: 4: + IC(0.886 ns) + CELL(0.178 ns) = 5.031 ns; Loc. = LCCOMB_X29_Y15_N26; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~296'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.178 ns) 6.347 ns lab5stopwatch:u1\|d3_reg\[0\]~297 5 COMB LCCOMB_X27_Y16_N4 1 " "Info: 5: + IC(1.138 ns) + CELL(0.178 ns) = 6.347 ns; Loc. = LCCOMB_X27_Y16_N4; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[0\]~297'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.443 ns lab5stopwatch:u1\|d3_reg\[0\] 6 REG LCFF_X27_Y16_N5 11 " "Info: 6: + IC(0.000 ns) + CELL(0.096 ns) = 6.443 ns; Loc. = LCFF_X27_Y16_N5; Fanout = 11; REG Node = 'lab5stopwatch:u1\|d3_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.151 ns ( 33.39 % ) " "Info: Total cell delay = 2.151 ns ( 33.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.292 ns ( 66.61 % ) " "Info: Total interconnect delay = 4.292 ns ( 66.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { up1 lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { up1 {} up1~combout {} lab5stopwatch:u1|d2_next~1381 {} lab5stopwatch:u1|d3_reg[1]~295 {} lab5stopwatch:u1|d3_reg[1]~296 {} lab5stopwatch:u1|d3_reg[0]~297 {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 1.943ns 0.325ns 0.886ns 1.138ns 0.000ns } { 0.000ns 1.036ns 0.485ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.853 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 39 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 39; COMB Node = 'clk1~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns lab5stopwatch:u1\|d3_reg\[0\] 3 REG LCFF_X27_Y16_N5 11 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X27_Y16_N5; Fanout = 11; REG Node = 'lab5stopwatch:u1\|d3_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { up1 lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { up1 {} up1~combout {} lab5stopwatch:u1|d2_next~1381 {} lab5stopwatch:u1|d3_reg[1]~295 {} lab5stopwatch:u1|d3_reg[1]~296 {} lab5stopwatch:u1|d3_reg[0]~297 {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 1.943ns 0.325ns 0.886ns 1.138ns 0.000ns } { 0.000ns 1.036ns 0.485ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk1 clk1~clkctrl lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} lab5stopwatch:u1|d3_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 sseg4\[1\] lab5stopwatch:u1\|d3_reg\[2\] 11.167 ns register " "Info: tco from clock \"clk1\" to destination pin \"sseg4\[1\]\" through register \"lab5stopwatch:u1\|d3_reg\[2\]\" is 11.167 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.859 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 2.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/