prev_cmp_lab5.qmsg

秒表可计时

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.658 ns register register " "Info: Estimated most critical path is register to register delay of 8.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lab5stopwatch:u1\|d2_reg\[1\] 1 REG LAB_X15_Y16 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y16; Fanout = 13; REG Node = 'lab5stopwatch:u1\|d2_reg\[1\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lab5stopwatch:u1|d2_reg[1] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.382 ns) + CELL(0.177 ns) 2.559 ns lab5stopwatch:u1\|Equal5~30 2 COMB LAB_X1_Y24 2 " "Info: 2: + IC(2.382 ns) + CELL(0.177 ns) = 2.559 ns; Loc. = LAB_X1_Y24; Fanout = 2; COMB Node = 'lab5stopwatch:u1\|Equal5~30'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.559 ns" { lab5stopwatch:u1|d2_reg[1] lab5stopwatch:u1|Equal5~30 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.198 ns) + CELL(0.322 ns) 5.079 ns lab5stopwatch:u1\|d2_next~1381 3 COMB LAB_X29_Y16 8 " "Info: 3: + IC(2.198 ns) + CELL(0.322 ns) = 5.079 ns; Loc. = LAB_X29_Y16; Fanout = 8; COMB Node = 'lab5stopwatch:u1\|d2_next~1381'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.520 ns" { lab5stopwatch:u1|Equal5~30 lab5stopwatch:u1|d2_next~1381 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.154 ns) + CELL(0.521 ns) 5.754 ns lab5stopwatch:u1\|d3_reg\[1\]~295 4 COMB LAB_X29_Y16 4 " "Info: 4: + IC(0.154 ns) + CELL(0.521 ns) = 5.754 ns; Loc. = LAB_X29_Y16; Fanout = 4; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~295'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.545 ns) 7.005 ns lab5stopwatch:u1\|d3_reg\[1\]~296 5 COMB LAB_X29_Y15 1 " "Info: 5: + IC(0.706 ns) + CELL(0.545 ns) = 7.005 ns; Loc. = LAB_X29_Y15; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[1\]~296'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.251 ns" { lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.521 ns) 8.562 ns lab5stopwatch:u1\|d3_reg\[0\]~297 6 COMB LAB_X27_Y16 1 " "Info: 6: + IC(1.036 ns) + CELL(0.521 ns) = 8.562 ns; Loc. = LAB_X27_Y16; Fanout = 1; COMB Node = 'lab5stopwatch:u1\|d3_reg\[0\]~297'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.557 ns" { lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 8.658 ns lab5stopwatch:u1\|d3_reg\[0\] 7 REG LAB_X27_Y16 11 " "Info: 7: + IC(0.000 ns) + CELL(0.096 ns) = 8.658 ns; Loc. = LAB_X27_Y16; Fanout = 11; REG Node = 'lab5stopwatch:u1\|d3_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } } { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.182 ns ( 25.20 % ) " "Info: Total cell delay = 2.182 ns ( 25.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.476 ns ( 74.80 % ) " "Info: Total interconnect delay = 6.476 ns ( 74.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "8.658 ns" { lab5stopwatch:u1|d2_reg[1] lab5stopwatch:u1|Equal5~30 lab5stopwatch:u1|d2_next~1381 lab5stopwatch:u1|d3_reg[1]~295 lab5stopwatch:u1|d3_reg[1]~296 lab5stopwatch:u1|d3_reg[0]~297 lab5stopwatch:u1|d3_reg[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}