prev_cmp_lab5.qmsg

秒表可计时

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 14 14:40:27 2008 " "Info: Processing started: Tue Oct 14 14:40:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lab5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lab5-one " "Info: Found design unit 1: lab5-one" {  } { { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lab5 " "Info: Found entity 1: lab5" {  } { { "lab5.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab5stopwatch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lab5stopwatch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lab5stopwatch-cascade_arch " "Info: Found design unit 1: lab5stopwatch-cascade_arch" {  } { { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lab5stopwatch " "Info: Found entity 1: lab5stopwatch" {  } { { "lab5stopwatch.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5stopwatch.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lab5 " "Info: Elaborating entity \"lab5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lab5stopwatch lab5stopwatch:u1 " "Info: Elaborating entity \"lab5stopwatch\" for hierarchy \"lab5stopwatch:u1\"" {  } { { "lab5.vhd" "u1" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "bin2led.vhd 2 1 " "Warning: Using design file bin2led.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bin2led-arch " "Info: Found design unit 1: bin2led-arch" {  } { { "bin2led.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/bin2led.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bin2led " "Info: Found entity 1: bin2led" {  } { { "bin2led.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/bin2led.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2led bin2led:u2 " "Info: Elaborating entity \"bin2led\" for hierarchy \"bin2led:u2\"" {  } { { "lab5.vhd" "u2" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vhd" 31 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "161 " "Info: Implemented 161 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "129 " "Info: Implemented 129 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Peak virtual memory: 182 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 14 14:40:34 2008 " "Info: Processing ended: Tue Oct 14 14:40:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}