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📄 lab5.sim.rpt

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; |lab5|lab5stopwatch:u1|d3_reg[1]       ; |lab5|lab5stopwatch:u1|d3_reg[1]       ; regout           ;
; |lab5|lab5stopwatch:u1|d3_reg[2]       ; |lab5|lab5stopwatch:u1|d3_reg[2]       ; regout           ;
; |lab5|lab5stopwatch:u1|d3_reg[3]       ; |lab5|lab5stopwatch:u1|d3_reg[3]       ; regout           ;
; |lab5|bin2led:u5|Mux6~13               ; |lab5|bin2led:u5|Mux6~13               ; combout          ;
; |lab5|bin2led:u5|Mux5~17               ; |lab5|bin2led:u5|Mux5~17               ; combout          ;
; |lab5|bin2led:u5|Mux4~13               ; |lab5|bin2led:u5|Mux4~13               ; combout          ;
; |lab5|bin2led:u5|Mux3~15               ; |lab5|bin2led:u5|Mux3~15               ; combout          ;
; |lab5|bin2led:u5|Mux2~17               ; |lab5|bin2led:u5|Mux2~17               ; combout          ;
; |lab5|bin2led:u5|Mux1~15               ; |lab5|bin2led:u5|Mux1~15               ; combout          ;
; |lab5|bin2led:u5|Mux0~13               ; |lab5|bin2led:u5|Mux0~13               ; combout          ;
; |lab5|lab5stopwatch:u1|Equal0~233      ; |lab5|lab5stopwatch:u1|Equal0~233      ; combout          ;
; |lab5|lab5stopwatch:u1|Equal0~234      ; |lab5|lab5stopwatch:u1|Equal0~234      ; combout          ;
; |lab5|lab5stopwatch:u1|Equal0~235      ; |lab5|lab5stopwatch:u1|Equal0~235      ; combout          ;
; |lab5|lab5stopwatch:u1|Equal0~236      ; |lab5|lab5stopwatch:u1|Equal0~236      ; combout          ;
; |lab5|lab5stopwatch:u1|Equal0~237      ; |lab5|lab5stopwatch:u1|Equal0~237      ; combout          ;
; |lab5|lab5stopwatch:u1|d1d_en~29       ; |lab5|lab5stopwatch:u1|d1d_en~29       ; combout          ;
; |lab5|lab5stopwatch:u1|d1_en~18        ; |lab5|lab5stopwatch:u1|d1_en~18        ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next~5       ; |lab5|lab5stopwatch:u1|d1_next~5       ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[3]~884  ; |lab5|lab5stopwatch:u1|d0_next[3]~884  ; combout          ;
; |lab5|lab5stopwatch:u1|d1d_en~30       ; |lab5|lab5stopwatch:u1|d1d_en~30       ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[2]~1151 ; |lab5|lab5stopwatch:u1|d1_next[2]~1151 ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[0]~885  ; |lab5|lab5stopwatch:u1|d0_next[0]~885  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[1]~886  ; |lab5|lab5stopwatch:u1|d0_next[1]~886  ; combout          ;
; |lab5|lab5stopwatch:u1|d1d_en~31       ; |lab5|lab5stopwatch:u1|d1d_en~31       ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[2]~887  ; |lab5|lab5stopwatch:u1|d0_next[2]~887  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[1]~888  ; |lab5|lab5stopwatch:u1|d0_next[1]~888  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[2]~889  ; |lab5|lab5stopwatch:u1|d0_next[2]~889  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[2]~890  ; |lab5|lab5stopwatch:u1|d0_next[2]~890  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[3]~891  ; |lab5|lab5stopwatch:u1|d0_next[3]~891  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[3]~892  ; |lab5|lab5stopwatch:u1|d0_next[3]~892  ; combout          ;
; |lab5|lab5stopwatch:u1|d0_next[3]~893  ; |lab5|lab5stopwatch:u1|d0_next[3]~893  ; combout          ;
; |lab5|lab5stopwatch:u1|Add3~268        ; |lab5|lab5stopwatch:u1|Add3~268        ; combout          ;
; |lab5|lab5stopwatch:u1|d2d_en~23       ; |lab5|lab5stopwatch:u1|d2d_en~23       ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next~12      ; |lab5|lab5stopwatch:u1|d1_next~12      ; combout          ;
; |lab5|lab5stopwatch:u1|d2_en~39        ; |lab5|lab5stopwatch:u1|d2_en~39        ; combout          ;
; |lab5|lab5stopwatch:u1|d2_en~40        ; |lab5|lab5stopwatch:u1|d2_en~40        ; combout          ;
; |lab5|lab5stopwatch:u1|d2_en~41        ; |lab5|lab5stopwatch:u1|d2_en~41        ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next~19      ; |lab5|lab5stopwatch:u1|d1_next~19      ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[0]~1152 ; |lab5|lab5stopwatch:u1|d1_next[0]~1152 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[1]~1153 ; |lab5|lab5stopwatch:u1|d1_next[1]~1153 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[1]~1154 ; |lab5|lab5stopwatch:u1|d1_next[1]~1154 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[2]~1155 ; |lab5|lab5stopwatch:u1|d1_next[2]~1155 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[2]~1156 ; |lab5|lab5stopwatch:u1|d1_next[2]~1156 ; combout          ;
; |lab5|lab5stopwatch:u1|Add3~269        ; |lab5|lab5stopwatch:u1|Add3~269        ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[3]~1157 ; |lab5|lab5stopwatch:u1|d1_next[3]~1157 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[3]~1158 ; |lab5|lab5stopwatch:u1|d1_next[3]~1158 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next[3]~1159 ; |lab5|lab5stopwatch:u1|d1_next[3]~1159 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next~1379    ; |lab5|lab5stopwatch:u1|d2_next~1379    ; combout          ;
; |lab5|lab5stopwatch:u1|Equal6~38       ; |lab5|lab5stopwatch:u1|Equal6~38       ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[1]~1380 ; |lab5|lab5stopwatch:u1|d2_next[1]~1380 ; combout          ;
; |lab5|lab5stopwatch:u1|Equal5~30       ; |lab5|lab5stopwatch:u1|Equal5~30       ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next~1381    ; |lab5|lab5stopwatch:u1|d2_next~1381    ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next~1382    ; |lab5|lab5stopwatch:u1|d2_next~1382    ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[0]~1383 ; |lab5|lab5stopwatch:u1|d2_next[0]~1383 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next~1160    ; |lab5|lab5stopwatch:u1|d1_next~1160    ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[1]~1384 ; |lab5|lab5stopwatch:u1|d2_next[1]~1384 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[1]~1385 ; |lab5|lab5stopwatch:u1|d2_next[1]~1385 ; combout          ;
; |lab5|lab5stopwatch:u1|d1_next~1161    ; |lab5|lab5stopwatch:u1|d1_next~1161    ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[2]~1386 ; |lab5|lab5stopwatch:u1|d2_next[2]~1386 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[2]~1387 ; |lab5|lab5stopwatch:u1|d2_next[2]~1387 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[2]~1388 ; |lab5|lab5stopwatch:u1|d2_next[2]~1388 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[2]~1389 ; |lab5|lab5stopwatch:u1|d2_next[2]~1389 ; combout          ;
; |lab5|lab5stopwatch:u1|Add5~260        ; |lab5|lab5stopwatch:u1|Add5~260        ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next~1390    ; |lab5|lab5stopwatch:u1|d2_next~1390    ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[3]~1391 ; |lab5|lab5stopwatch:u1|d2_next[3]~1391 ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[3]~1392 ; |lab5|lab5stopwatch:u1|d2_next[3]~1392 ; combout          ;
; |lab5|lab5stopwatch:u1|d3_reg[1]~293   ; |lab5|lab5stopwatch:u1|d3_reg[1]~293   ; combout          ;
; |lab5|lab5stopwatch:u1|d3_reg[1]~294   ; |lab5|lab5stopwatch:u1|d3_reg[1]~294   ; combout          ;
; |lab5|lab5stopwatch:u1|d3_next~154     ; |lab5|lab5stopwatch:u1|d3_next~154     ; combout          ;
; |lab5|lab5stopwatch:u1|d3_reg[1]~295   ; |lab5|lab5stopwatch:u1|d3_reg[1]~295   ; combout          ;
; |lab5|lab5stopwatch:u1|d3_next~155     ; |lab5|lab5stopwatch:u1|d3_next~155     ; combout          ;
; |lab5|lab5stopwatch:u1|d3_reg[1]~296   ; |lab5|lab5stopwatch:u1|d3_reg[1]~296   ; combout          ;
; |lab5|lab5stopwatch:u1|d3_reg[0]~297   ; |lab5|lab5stopwatch:u1|d3_reg[0]~297   ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~222        ; |lab5|lab5stopwatch:u1|Add8~222        ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~223        ; |lab5|lab5stopwatch:u1|Add8~223        ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~224        ; |lab5|lab5stopwatch:u1|Add8~224        ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~227        ; |lab5|lab5stopwatch:u1|Add8~227        ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~230        ; |lab5|lab5stopwatch:u1|Add8~230        ; combout          ;
; |lab5|lab5stopwatch:u1|Add8~231        ; |lab5|lab5stopwatch:u1|Add8~231        ; combout          ;
; |lab5|lab5stopwatch:u1|ms_next~24      ; |lab5|lab5stopwatch:u1|ms_next~24      ; combout          ;
; |lab5|lab5stopwatch:u1|d2_next[2]~1393 ; |lab5|lab5stopwatch:u1|d2_next[2]~1393 ; combout          ;
; |lab5|sseg1[0]                         ; |lab5|sseg1[0]                         ; padio            ;
; |lab5|sseg1[1]                         ; |lab5|sseg1[1]                         ; padio            ;
; |lab5|sseg1[2]                         ; |lab5|sseg1[2]                         ; padio            ;
; |lab5|sseg1[3]                         ; |lab5|sseg1[3]                         ; padio            ;
; |lab5|sseg1[4]                         ; |lab5|sseg1[4]                         ; padio            ;
; |lab5|sseg1[5]                         ; |lab5|sseg1[5]                         ; padio            ;
; |lab5|sseg1[6]                         ; |lab5|sseg1[6]                         ; padio            ;
; |lab5|sseg2[0]                         ; |lab5|sseg2[0]                         ; padio            ;
; |lab5|sseg2[1]                         ; |lab5|sseg2[1]                         ; padio            ;
; |lab5|sseg2[2]                         ; |lab5|sseg2[2]                         ; padio            ;
; |lab5|sseg2[3]                         ; |lab5|sseg2[3]                         ; padio            ;
; |lab5|sseg2[4]                         ; |lab5|sseg2[4]                         ; padio            ;
; |lab5|sseg2[5]                         ; |lab5|sseg2[5]                         ; padio            ;
; |lab5|sseg2[6]                         ; |lab5|sseg2[6]                         ; padio            ;
; |lab5|sseg3[0]                         ; |lab5|sseg3[0]                         ; padio            ;
; |lab5|sseg3[1]                         ; |lab5|sseg3[1]                         ; padio            ;
; |lab5|sseg3[2]                         ; |lab5|sseg3[2]                         ; padio            ;
; |lab5|sseg3[3]                         ; |lab5|sseg3[3]                         ; padio            ;
; |lab5|sseg3[4]                         ; |lab5|sseg3[4]                         ; padio            ;
; |lab5|sseg3[5]                         ; |lab5|sseg3[5]                         ; padio            ;
; |lab5|sseg3[6]                         ; |lab5|sseg3[6]                         ; padio            ;
; |lab5|sseg4[0]                         ; |lab5|sseg4[0]                         ; padio            ;
; |lab5|sseg4[1]                         ; |lab5|sseg4[1]                         ; padio            ;
; |lab5|sseg4[2]                         ; |lab5|sseg4[2]                         ; padio            ;
; |lab5|sseg4[3]                         ; |lab5|sseg4[3]                         ; padio            ;
; |lab5|sseg4[4]                         ; |lab5|sseg4[4]                         ; padio            ;
; |lab5|sseg4[5]                         ; |lab5|sseg4[5]                         ; padio            ;
; |lab5|sseg4[6]                         ; |lab5|sseg4[6]                         ; padio            ;
; |lab5|up1                              ; |lab5|up1~corein                       ; combout          ;
; |lab5|clr1                             ; |lab5|clr1~corein                      ; combout          ;
; |lab5|go1                              ; |lab5|go1~corein                       ; combout          ;
+----------------------------------------+----------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Oct 14 14:45:42 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lab5 -c lab5
Info: Using vector source file "G:/EEC 587 Rapid Digital System Prototyping/VHDL/lab5/lab5.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      11.56 %
Info: Number of transitions in simulation is 1450
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 114 megabytes
    Info: Processing ended: Tue Oct 14 14:45:44 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


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