lab5stopwatch.vhd

秒表可计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5stopwatch is
  port(
       up, clk: in std_logic;
       go, clr: in std_logic;
       d3, d2, d1, d0:out std_logic_vector(3 downto 0)
);
end lab5stopwatch;

architecture cascade_arch of lab5stopwatch is
  constant DVSR: integer:=5000000;
  signal ms_reg, ms_next:unsigned(22 downto 0);
  signal d3_reg, d2_reg, d1_reg, d0_reg:unsigned(3 downto 0);
  signal d3_next, d2_next, d1_next, d0_next:unsigned(3 downto 0);
  signal d1_en, d2_en, d3_en, d0_en:std_logic;
  signal d1d_en, d2d_en, d3d_en, d0d_en:std_logic;
  signal ms_tick, d0_tick, d1_tick, d2_tick: std_logic;
  signal d0d_tick, d1d_tick, d2d_tick: std_logic;
begin
  process(clk)
  begin 
     if(clk'event and clk='1') then
        ms_reg<=ms_next;
        d3_reg<=d3_next;
        d2_reg<=d2_next;
        d1_reg<=d1_next;
        d0_reg<=d0_next;
     end if;
  end process;
  
  ms_next<=
        (others=>'0') when clr='1' or (ms_reg=DVSR and go='1') else
        ms_reg+1     when go='1'  else
        ms_reg;
  ms_tick<='1' when ms_reg=DVSR else '0';

----0.1 sec counter
  d0_en<='1' when ms_tick='1' else '0';
  d0_next<=
         "0000" when (clr='1') or (d0_en='1' and d0_reg=9 and up='1') else
         "1001" when (clr='1') or (d0_en='1' and d0_reg=0 and up='0') else
         d0_reg+1 when (d0_en='1') and (up='1') else
         d0_reg-1 when (d0_en='1') and (up='0') else
         d0_reg;
  d0_tick<='1' when d0_reg=9 else '0';
d0d_tick<='1' when d0_reg=0 else '0';

----1 sec counter
  d1_en<='1' when ms_tick='1' and d0_tick='1' else '0';
d1d_en<='1' when ms_tick='1' and d0d_tick='1' else '0';
  d1_next<=
         "0000" when (clr='1') or (d1_en='1' and d1_reg=9 and up='1') else
         "1001" when (clr='1') or (d1d_en='1' and d1_reg=0 and up='0') else
         d1_reg+1 when (d1_en='1') and (up='1') else
         d1_reg-1 when (d1d_en='1') and (up='0') else
         d1_reg;
  d1_tick<='1' when d1_reg=9 else '0';  
  d1d_tick<='1' when d1_reg=0 else '0'; 

-----10 sec counter
  d2_en<=
         '1' when ms_tick='1' and d0_tick='1' and d1_tick='1' else 
         '0';
  d2d_en<=
         '1' when ms_tick='1' and d0d_tick='1' and d1d_tick='1' else 
         '0';
  d2_next<=
         "0000" when (clr='1') or (d2_en='1' and d2_reg=5 and up='1') else
         "0101" when (clr='1') or (d2d_en='1' and d2_reg=0 and up='0') else         
         d2_reg+1 when (d2_en='1') and (up='1') else
         d2_reg-1 when (d2d_en='1') and (up='0') else
         d2_reg;
  d2_tick<='1' when d2_reg=5 else '0'; 
  d2d_tick<='1' when d2_reg=0 else '0'; 


------1 min counter
  d3_en<=
         '1' when ms_tick='1' and d0_tick='1' and d1_tick='1' and d2_tick='1' else 
         '0';
  d3d_en<=
         '1' when ms_tick='1' and d0d_tick='1' and d1d_tick='1' and d2d_tick='1' else 
         '0';
  d3_next<=
         "0000" when (clr='1') or (d3_en='1' and d3_reg=9 and up='1') else
         "1001" when (clr='1') or (d3d_en='1' and d3_reg=0 and up='0') else         
         d3_reg+1 when (d3_en='1') and (up='1') else
         d3_reg-1 when (d3d_en='1') and (up='0') else
         d3_reg;



  d0<=std_logic_vector(d0_reg);
  d1<=std_logic_vector(d1_reg);
  d2<=std_logic_vector(d2_reg);
  d3<=std_logic_vector(d3_reg); 
end cascade_arch;