lab5.vhd

来自「秒表可计时」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
entity lab5 is
port(
       up1, clk1: in std_logic;
       go1, clr1: in std_logic; 
     sseg1,sseg2,sseg3,sseg4:out std_logic_vector(6 downto 0)
);
end lab5;

architecture one of lab5 is
COMPONENT bin2led 
  port(
      bin: in std_logic_vector(3 downto 0);
      sseg: out std_logic_vector(6 downto 0)
   );

end COMPONENT;

COMPONENT lab5stopwatch  
  port(
       up, clk: in std_logic;
       go, clr: in std_logic;
       d3, d2, d1, d0:out std_logic_vector(3 downto 0)
);
end COMPONENT;

signal a,b,c,d: std_logic_vector(3 downto 0);
begin
u1: lab5stopwatch port map(up=>up1, clk=>clk1, clr=>clr1,go=>go1, d0=>a,d1=>b,d2=>c,d3=>d);
u2: bin2led port map(bin=>a, sseg=>sseg1);
u3: bin2led port map(bin=>b, sseg=>sseg2);
u4: bin2led port map(bin=>c, sseg=>sseg3);
u5: bin2led port map(bin=>d, sseg=>sseg4);
end one;