median.tan.qmsg

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register a2\[4\]~reg0 register d0\[7\] 154.2 MHz 6.485 ns Internal " "Info: Clock \"clk\" has Internal fmax of 154.2 MHz between source register \"a2\[4\]~reg0\" and destination register \"d0\[7\]\" (period= 6.485 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.245 ns + Longest register register " "Info: + Longest register to register delay is 6.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a2\[4\]~reg0 1 REG LCFF_X30_Y14_N3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y14_N3; Fanout = 7; REG Node = 'a2\[4\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a2[4]~reg0 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.585 ns) + CELL(0.495 ns) 2.080 ns LessThan1~113 2 COMB LCCOMB_X32_Y14_N24 1 " "Info: 2: + IC(1.585 ns) + CELL(0.495 ns) = 2.080 ns; Loc. = LCCOMB_X32_Y14_N24; Fanout = 1; COMB Node = 'LessThan1~113'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { a2[4]~reg0 LessThan1~113 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.160 ns LessThan1~115 3 COMB LCCOMB_X32_Y14_N26 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.160 ns; Loc. = LCCOMB_X32_Y14_N26; Fanout = 1; COMB Node = 'LessThan1~115'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { LessThan1~113 LessThan1~115 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.240 ns LessThan1~117 4 COMB LCCOMB_X32_Y14_N28 1 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.240 ns; Loc. = LCCOMB_X32_Y14_N28; Fanout = 1; COMB Node = 'LessThan1~117'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { LessThan1~115 LessThan1~117 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 2.698 ns LessThan1~118 5 COMB LCCOMB_X32_Y14_N30 16 " "Info: 5: + IC(0.000 ns) + CELL(0.458 ns) = 2.698 ns; Loc. = LCCOMB_X32_Y14_N30; Fanout = 16; COMB Node = 'LessThan1~118'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { LessThan1~117 LessThan1~118 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.912 ns) + CELL(0.178 ns) 3.788 ns Add1~279 6 COMB LCCOMB_X29_Y14_N28 2 " "Info: 6: + IC(0.912 ns) + CELL(0.178 ns) = 3.788 ns; Loc. = LCCOMB_X29_Y14_N28; Fanout = 2; COMB Node = 'Add1~279'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.090 ns" { LessThan1~118 Add1~279 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.517 ns) 5.117 ns d0\[0\]~1146 7 COMB LCCOMB_X29_Y14_N12 2 " "Info: 7: + IC(0.812 ns) + CELL(0.517 ns) = 5.117 ns; Loc. = LCCOMB_X29_Y14_N12; Fanout = 2; COMB Node = 'd0\[0\]~1146'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.329 ns" { Add1~279 d0[0]~1146 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 5.291 ns d0\[1\]~1148 8 COMB LCCOMB_X29_Y14_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.174 ns) = 5.291 ns; Loc. = LCCOMB_X29_Y14_N14; Fanout = 2; COMB Node = 'd0\[1\]~1148'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { d0[0]~1146 d0[1]~1148 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.371 ns d0\[2\]~1150 9 COMB LCCOMB_X29_Y14_N16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 5.371 ns; Loc. = LCCOMB_X29_Y14_N16; Fanout = 2; COMB Node = 'd0\[2\]~1150'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d0[1]~1148 d0[2]~1150 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.451 ns d0\[3\]~1152 10 COMB LCCOMB_X29_Y14_N18 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 5.451 ns; Loc. = LCCOMB_X29_Y14_N18; Fanout = 2; COMB Node = 'd0\[3\]~1152'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d0[2]~1150 d0[3]~1152 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.531 ns d0\[4\]~1154 11 COMB LCCOMB_X29_Y14_N20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 5.531 ns; Loc. = LCCOMB_X29_Y14_N20; Fanout = 2; COMB Node = 'd0\[4\]~1154'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d0[3]~1152 d0[4]~1154 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.611 ns d0\[5\]~1156 12 COMB LCCOMB_X29_Y14_N22 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 5.611 ns; Loc. = LCCOMB_X29_Y14_N22; Fanout = 2; COMB Node = 'd0\[5\]~1156'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d0[4]~1154 d0[5]~1156 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.691 ns d0\[6\]~1158 13 COMB LCCOMB_X29_Y14_N24 1 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 5.691 ns; Loc. = LCCOMB_X29_Y14_N24; Fanout = 1; COMB Node = 'd0\[6\]~1158'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d0[5]~1156 d0[6]~1158 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.149 ns d0\[7\]~1159 14 COMB LCCOMB_X29_Y14_N26 1 " "Info: 14: + IC(0.000 ns) + CELL(0.458 ns) = 6.149 ns; Loc. = LCCOMB_X29_Y14_N26; Fanout = 1; COMB Node = 'd0\[7\]~1159'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { d0[6]~1158 d0[7]~1159 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.245 ns d0\[7\] 15 REG LCFF_X29_Y14_N27 1 " "Info: 15: + IC(0.000 ns) + CELL(0.096 ns) = 6.245 ns; Loc. = LCFF_X29_Y14_N27; Fanout = 1; REG Node = 'd0\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { d0[7]~1159 d0[7] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.936 ns ( 47.01 % ) " "Info: Total cell delay = 2.936 ns ( 47.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.309 ns ( 52.99 % ) " "Info: Total interconnect delay = 3.309 ns ( 52.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { a2[4]~reg0 LessThan1~113 LessThan1~115 LessThan1~117 LessThan1~118 Add1~279 d0[0]~1146 d0[1]~1148 d0[2]~1150 d0[3]~1152 d0[4]~1154 d0[5]~1156 d0[6]~1158 d0[7]~1159 d0[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { a2[4]~reg0 {} LessThan1~113 {} LessThan1~115 {} LessThan1~117 {} LessThan1~118 {} Add1~279 {} d0[0]~1146 {} d0[1]~1148 {} d0[2]~1150 {} d0[3]~1152 {} d0[4]~1154 {} d0[5]~1156 {} d0[6]~1158 {} d0[7]~1159 {} d0[7] {} } { 0.000ns 1.585ns 0.000ns 0.000ns 0.000ns 0.912ns 0.812ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.861 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 526 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 526; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 2.861 ns d0\[7\] 3 REG LCFF_X29_Y14_N27 1 " "Info: 3: + IC(0.995 ns) + CELL(0.602 ns) = 2.861 ns; Loc. = LCFF_X29_Y14_N27; Fanout = 1; REG Node = 'd0\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { clk~clkctrl d0[7] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.90 % ) " "Info: Total cell delay = 1.628 ns ( 56.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.233 ns ( 43.10 % ) " "Info: Total interconnect delay = 1.233 ns ( 43.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl d0[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk {} clk~combout {} clk~clkctrl {} d0[7] {} } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.862 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 526 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 526; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 2.862 ns a2\[4\]~reg0 3 REG LCFF_X30_Y14_N3 7 " "Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X30_Y14_N3; Fanout = 7; REG Node = 'a2\[4\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk~clkctrl a2[4]~reg0 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.88 % ) " "Info: Total cell delay = 1.628 ns ( 56.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 43.12 % ) " "Info: Total interconnect delay = 1.234 ns ( 43.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl a2[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} a2[4]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl d0[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk {} clk~combout {} clk~clkctrl {} d0[7] {} } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl a2[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} a2[4]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { a2[4]~reg0 LessThan1~113 LessThan1~115 LessThan1~117 LessThan1~118 Add1~279 d0[0]~1146 d0[1]~1148 d0[2]~1150 d0[3]~1152 d0[4]~1154 d0[5]~1156 d0[6]~1158 d0[7]~1159 d0[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { a2[4]~reg0 {} LessThan1~113 {} LessThan1~115 {} LessThan1~117 {} LessThan1~118 {} Add1~279 {} d0[0]~1146 {} d0[1]~1148 {} d0[2]~1150 {} d0[3]~1152 {} d0[4]~1154 {} d0[5]~1156 {} d0[6]~1158 {} d0[7]~1159 {} d0[7] {} } { 0.000ns 1.585ns 0.000ns 0.000ns 0.000ns 0.912ns 0.812ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl d0[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk {} clk~combout {} clk~clkctrl {} d0[7] {} } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl a2[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} a2[4]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "addr\[2\] load clk 8.642 ns register " "Info: tsu for register \"addr\[2\]\" (data pin = \"load\", clock pin = \"clk\") is 8.642 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.545 ns + Longest pin register " "Info: + Longest pin to register delay is 11.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.853 ns) 0.853 ns load 1 PIN PIN_H13 34 " "Info: 1: + IC(0.000 ns) + CELL(0.853 ns) = 0.853 ns; Loc. = PIN_H13; Fanout = 34; PIN Node = 'load'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { load } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.182 ns) + CELL(0.542 ns) 7.577 ns img_x\[10\]~892 2 COMB LCCOMB_X35_Y17_N0 28 " "Info: 2: + IC(6.182 ns) + CELL(0.542 ns) = 7.577 ns; Loc. = LCCOMB_X35_Y17_N0; Fanout = 28; COMB Node = 'img_x\[10\]~892'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.724 ns" { load img_x[10]~892 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.322 ns) 8.831 ns addr\[0\]~864 3 COMB LCCOMB_X36_Y13_N16 1 " "Info: 3: + IC(0.932 ns) + CELL(0.322 ns) = 8.831 ns; Loc. = LCCOMB_X36_Y13_N16; Fanout = 1; COMB Node = 'addr\[0\]~864'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.254 ns" { img_x[10]~892 addr[0]~864 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.178 ns) 9.888 ns addr\[0\]~865 4 COMB LCCOMB_X36_Y14_N8 11 " "Info: 4: + IC(0.879 ns) + CELL(0.178 ns) = 9.888 ns; Loc. = LCCOMB_X36_Y14_N8; Fanout = 11; COMB Node = 'addr\[0\]~865'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.057 ns" { addr[0]~864 addr[0]~865 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.758 ns) 11.545 ns addr\[2\] 5 REG LCFF_X36_Y13_N11 12 " "Info: 5: + IC(0.899 ns) + CELL(0.758 ns) = 11.545 ns; Loc. = LCFF_X36_Y13_N11; Fanout = 12; REG Node = 'addr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { addr[0]~865 addr[2] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.653 ns ( 22.98 % ) " "Info: Total cell delay = 2.653 ns ( 22.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.892 ns ( 77.02 % ) " "Info: Total interconnect delay = 8.892 ns ( 77.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.545 ns" { load img_x[10]~892 addr[0]~864 addr[0]~865 addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.545 ns" { load {} load~combout {} img_x[10]~892 {} addr[0]~864 {} addr[0]~865 {} addr[2] {} } { 0.000ns 0.000ns 6.182ns 0.932ns 0.879ns 0.899ns } { 0.000ns 0.853ns 0.542ns 0.322ns 0.178ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.865 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 526 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 526; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.602 ns) 2.865 ns addr\[2\] 3 REG LCFF_X36_Y13_N11 12 " "Info: 3: + IC(0.999 ns) + CELL(0.602 ns) = 2.865 ns; Loc. = LCFF_X36_Y13_N11; Fanout = 12; REG Node = 'addr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { clk~clkctrl addr[2] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.82 % ) " "Info: Total cell delay = 1.628 ns ( 56.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.237 ns ( 43.18 % ) " "Info: Total interconnect delay = 1.237 ns ( 43.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { clk {} clk~combout {} clk~clkctrl {} addr[2] {} } { 0.000ns 0.000ns 0.238ns 0.999ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.545 ns" { load img_x[10]~892 addr[0]~864 addr[0]~865 addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.545 ns" { load {} load~combout {} img_x[10]~892 {} addr[0]~864 {} addr[0]~865 {} addr[2] {} } { 0.000ns 0.000ns 6.182ns 0.932ns 0.879ns 0.899ns } { 0.000ns 0.853ns 0.542ns 0.322ns 0.178ns 0.758ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { clk {} clk~combout {} clk~clkctrl {} addr[2] {} } { 0.000ns 0.000ns 0.238ns 0.999ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk a3\[3\] a3\[3\]~reg0 10.342 ns register " "Info: tco from clock \"clk\" to destination pin \"a3\[3\]\" through register \"a3\[3\]~reg0\" is 10.342 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.864 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 526 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 526; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 2.864 ns a3\[3\]~reg0 3 REG LCFF_X33_Y14_N25 7 " "Info: 3: + IC(0.998 ns) + CELL(0.602 ns) = 2.864 ns; Loc. = LCFF_X33_Y14_N25; Fanout = 7; REG Node = 'a3\[3\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk~clkctrl a3[3]~reg0 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.84 % ) " "Info: Total cell delay = 1.628 ns ( 56.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.236 ns ( 43.16 % ) " "Info: Total interconnect delay = 1.236 ns ( 43.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { clk clk~clkctrl a3[3]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { clk {} clk~combout {} clk~clkctrl {} a3[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.201 ns + Longest register pin " "Info: + Longest register to pin delay is 7.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a3\[3\]~reg0 1 REG LCFF_X33_Y14_N25 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y14_N25; Fanout = 7; REG Node = 'a3\[3\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a3[3]~reg0 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.185 ns) + CELL(3.016 ns) 7.201 ns a3\[3\] 2 PIN PIN_AB17 0 " "Info: 2: + IC(4.185 ns) + CELL(3.016 ns) = 7.201 ns; Loc. = PIN_AB17; Fanout = 0; PIN Node = 'a3\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.201 ns" { a3[3]~reg0 a3[3] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.016 ns ( 41.88 % ) " "Info: Total cell delay = 3.016 ns ( 41.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.185 ns ( 58.12 % ) " "Info: Total interconnect delay = 4.185 ns ( 58.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.201 ns" { a3[3]~reg0 a3[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.201 ns" { a3[3]~reg0 {} a3[3] {} } { 0.000ns 4.185ns } { 0.000ns 3.016ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { clk clk~clkctrl a3[3]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { clk {} clk~combout {} clk~clkctrl {} a3[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.201 ns" { a3[3]~reg0 a3[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.201 ns" { a3[3]~reg0 {} a3[3] {} } { 0.000ns 4.185ns } { 0.000ns 3.016ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "q_min\[7\] reset clk -1.050 ns register " "Info: th for register \"q_min\[7\]\" (data pin = \"reset\", clock pin = \"clk\") is -1.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.858 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 526 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 526; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns q_min\[7\] 3 REG LCFF_X34_Y17_N3 2 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X34_Y17_N3; Fanout = 2; REG Node = 'q_min\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { clk~clkctrl q_min[7] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk clk~clkctrl q_min[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk {} clk~combout {} clk~clkctrl {} q_min[7] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.194 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.194 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns reset 1 PIN PIN_M2 15 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 15; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.816 ns) + CELL(0.322 ns) 3.164 ns q_min\[7\]~178 2 COMB LCCOMB_X34_Y17_N24 16 " "Info: 2: + IC(1.816 ns) + CELL(0.322 ns) = 3.164 ns; Loc. = LCCOMB_X34_Y17_N24; Fanout = 16; COMB Node = 'q_min\[7\]~178'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.138 ns" { reset q_min[7]~178 } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.272 ns) + CELL(0.758 ns) 4.194 ns q_min\[7\] 3 REG LCFF_X34_Y17_N3 2 " "Info: 3: + IC(0.272 ns) + CELL(0.758 ns) = 4.194 ns; Loc. = LCFF_X34_Y17_N3; Fanout = 2; REG Node = 'q_min\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.030 ns" { q_min[7]~178 q_min[7] } "NODE_NAME" } } { "median.v" "" { Text "I:/panjian9/median.v" 414 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.106 ns ( 50.21 % ) " "Info: Total cell delay = 2.106 ns ( 50.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.088 ns ( 49.79 % ) " "Info: Total interconnect delay = 2.088 ns ( 49.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.194 ns" { reset q_min[7]~178 q_min[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.194 ns" { reset {} reset~combout {} q_min[7]~178 {} q_min[7] {} } { 0.000ns 0.000ns 1.816ns 0.272ns } { 0.000ns 1.026ns 0.322ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk clk~clkctrl q_min[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk {} clk~combout {} clk~clkctrl {} q_min[7] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.194 ns" { reset q_min[7]~178 q_min[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.194 ns" { reset {} reset~combout {} q_min[7]~178 {} q_min[7] {} } { 0.000ns 0.000ns 1.816ns 0.272ns } { 0.000ns 1.026ns 0.322ns 0.758ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}