ycbcr_to_rgb_tb.v

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//
// This reference design file, and your use thereof, is subject to and governed
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/////////////////////////////////////////////////////////////////////////////

module ycbcr_to_rgb_tb ();

reg rst,clk;
reg [7:0] y,cb,cr;
wire [7:0] red,green,blue;

///////////////////////////////////////////
// test device

ycbcr_to_rgb dut (
	.y(y),.cb(cb),.cr(cr),
	.red(red),.green(green),.blue(blue),
	.clk(clk)
);

///////////////////////////////////////////
// reference formulas

real r,rp,rpp,g,gp,gpp,b,bp,bpp; 
real ry,rcr,rcb;
real c16 = 16;	// A Verilog type cast?
real c128 = 128; 

always @(posedge clk) begin
	ry <= y-c16;
	rcr <= cr-c128;
	rcb <= cb-c128;
	rpp <= 1.164 * ry + 1.596 * rcr;
	gpp <= 1.164 * ry - 0.813 * rcr - 0.392*rcb;
	bpp <= 1.164 * ry + 2.017 * rcb;
	rp <= rpp;
	gp <= gpp;
	bp <= bpp;
	r <= (rp < 0) ? 0 : (rp > 255) ? 255 : rp;
	g <= (gp < 0) ? 0 : (gp > 255) ? 255 : gp;
	b <= (bp < 0) ? 0 : (bp > 255) ? 255 : bp;	
end

real error_bar = 2;
real rdelta,gdelta,bdelta;

integer n = 0;
initial begin
	clk = 0;
	rst = 0;
	@(negedge clk) y = 255; cb = 255; cr = 255;
	@(negedge clk); @(negedge clk);

	@(negedge clk) y = 255; cb = 0; cr = 0;
	@(negedge clk); @(negedge clk);

	for (n=0; n<1000000; n=n+1) 
	begin
		@(negedge clk) y = $random; cb = $random; cr = $random;
		@(negedge clk); 
		@(negedge clk); 
		
		rdelta = r-red;
		gdelta = g-green;
		bdelta = b-blue;
		if ((rdelta > error_bar) | 
			(rdelta < -error_bar) |
			(gdelta > error_bar) | 
			(gdelta < -error_bar) |
			(bdelta > error_bar) | 
			(bdelta < -error_bar))
		begin
			$display ("Error margin too high at time %d", $time);
			#100
			$stop();
		end

	end

	$display ("PASS");
	$stop();
end

always begin
	#50 clk = ~clk;
end

endmodule