equal_const_tb.v

来自「本電子檔為 verilog cookbook,包含了通訊,影像,DSP等重要常用」· Verilog 代码 · 共 61 行

// Copyright 2007 Altera Corporation. All rights reserved.  
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/////////////////////////////////////////////////////////////////////////////

module equal_const_tb ();

parameter WIDTH = 10;
parameter CONST_VAL = 10'b1010111010;

reg [WIDTH-1:0] dat;
reg fail;

wire aa,bb;

equal_const a (.dat(dat),.out(aa));
	defparam a .WIDTH = WIDTH;
	defparam a .METHOD = 0;
	defparam a .CONST_VAL = CONST_VAL;

equal_const b (.dat(dat),.out(bb));
	defparam b .WIDTH = WIDTH;
	defparam b .METHOD = 1;
	defparam b .CONST_VAL = CONST_VAL;

initial begin
	dat = 0;
	fail = 0;

	#100000 if (!fail) $display ("PASS");
	$stop();
end


always begin
  #50 dat = {$random,$random};
	
  #50 if  (aa !== bb) begin
  		$display ("Mismatch at time %d",$time);
		fail = 1;
	end
end

endmodule