pipe_equal_tb.v

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// baeckler - 02-23-2006

module pipe_equal_tb ();

reg [63:0] ra;
reg [63:0] rb;
reg clk,rst,fail;

initial begin
  ra = 0;
  rb = 0;
  fail = 0;
  clk = 0;
  rst = 0;
  #10 rst = 1;
  #10 rst = 0;

  #100000
  if (!fail) $display ("PASS");
  $stop();
end

wire eq;
reg [2:0] lag;

always @(posedge clk) begin
  lag <= (lag << 1) | (ra == rb);
end

pipe_equal p (.rst(rst),.clk(clk),.a(ra),.b(rb),.eq(eq));

always begin
  #100 clk = ~clk;
end

// make the inputs equal a lot of the time
always @(negedge clk) begin
  if ($random & 1'b1) begin
    ra = {$random,$random};
	rb = {$random,$random};  
  end
  else begin
	rb = ra;  
  end
end

// check it
always @(posedge clk) begin
  #10 if (lag[2] == 1'b1 || lag[2] == 1'b0) begin
	if (lag[2] != eq) begin
		$display ("Mismatch at time %d",$time);
		fail = 1;
	end
  end
end

endmodule