mask_tb.v

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// Copyright 2007 Altera Corporation. All rights reserved.  
// Altera products are protected under numerous U.S. and foreign patents, 
// maskwork rights, copyrights and other intellectual property laws.  
//
// This reference design file, and your use thereof, is subject to and governed
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// License Agreement (either as signed by you or found at www.altera.com).  By
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// design file and please promptly destroy any copies you have made.
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// This reference design file is being provided on an "as-is" basis and as an 
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/////////////////////////////////////////////////////////////////////////////

module mask_tb ();

wire [15:0] mask,mask_b,mask_c;
reg [3:0] in;

mask_16 m16 (.in(in),.mask(mask));
mask_32 m32 (.in({1'b0,in}),.mask({mask_b,mask_c}));

initial begin 
  in=0;
end

// just a quick sanity check
reg fail = 0;
always begin
  #1000 in = in + 1;
  #10 if (mask !== mask_b || mask_c !== 0) begin
	  $display ("Mismatch at time %d",$time);
	  fail = 1'b1;
	end
  if (in == 15) begin
	if (!fail) $display ("PASS");
	$stop();
  end
end

endmodule