delay_reg_tb.v

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//
// This reference design file, and your use thereof, is subject to and governed
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/////////////////////////////////////////////////////////////////////////////

module delay_reg_tb ();

parameter DEPTH = 5;
parameter WIDTH = 64;

reg clock,enable;
reg [WIDTH-1:0] data_in;
wire [WIDTH-1:0] data_out;

/////////////////////
// test unit
/////////////////////
delay_reg dut (
	.clock (clock),
	.enable (enable),
	.data_in (data_in),
	.data_out (data_out)
);
defparam dut .DEPTH = DEPTH;
defparam dut .WIDTH = WIDTH;

/////////////////////
// reference unit
/////////////////////
reg [DEPTH*WIDTH-1:0] comp_reg;
always @(posedge clock) begin
	if (enable) comp_reg <= (comp_reg << WIDTH) | data_in;
end

/////////////////////
// stim
/////////////////////
initial begin
	clock = 1'b0;
	data_in = 0;
	enable = 1'b1;
end

always begin 
	#100 clock = ~clock;
end

always @(negedge clock) begin
	data_in = {$random,$random};
end

reg fail = 0;
always @(posedge clock) begin
	#10 if (comp_reg[DEPTH*WIDTH-1:DEPTH*WIDTH-WIDTH] !== data_out) begin
		$display ("Disagreement at time %d",$time);
		fail = 1'b1;
	end
end

initial begin
	#1000000
	if (!fail) $display("PASS");
	$stop();
end

endmodule