eight_to_one_tb.v

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module eight_to_one_tb ();

reg [7:0] dat;
reg [2:0] sel;
reg fail = 0;

wire out_a,out_b,out_c;

eight_to_one a (.dat(dat),.sel(sel),.out(out_a));
	defparam a .SEVEN_SEVEN_STYLE = 1;

eight_to_one b (.dat(dat),.sel(sel),.out(out_b));
	defparam b .FIVE_FIVE_STYLE = 1;

eight_to_one c (.dat(dat),.sel(sel),.out(out_c));

initial begin
	dat = 0;
	sel = 0;
	fail = 0;
	#1000000 
	if (!fail) $display ("PASS");
	$stop();
end

always begin
	#1000 dat = $random;
	sel = $random;
	#1000
	if (out_a != out_b || out_a != out_c) begin
		fail = 1;
		$display ("Mismatch at time %d",$time);
	end
end

endmodule