chk.tan.rpt

本设计是一个序列检测器

+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 17.300 ns  ; F$latch ; F  ; CLK        ;
; N/A   ; None         ; 16.200 ns  ; F$latch ; F  ; DaIN       ;
+-------+--------------+------------+---------+----+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; -0.800 ns ; DaIN ; CURRENT_STATE.st4 ; CLK      ;
; N/A           ; None        ; -0.800 ns ; DaIN ; CURRENT_STATE.st3 ; CLK      ;
; N/A           ; None        ; -0.800 ns ; DaIN ; CURRENT_STATE.st0 ; CLK      ;
; N/A           ; None        ; -0.900 ns ; DaIN ; CURRENT_STATE.st2 ; CLK      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 14 09:28:20 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CHK -c CHK
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "F$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "DaIN" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Selector3~3" as buffer
    Info: Detected ripple clock "CURRENT_STATE.st3" as buffer
    Info: Detected ripple clock "CURRENT_STATE.st4" as buffer
Info: Clock "CLK" has Internal fmax of 250.0 MHz between source register "CURRENT_STATE.st4" and destination register "F$latch" (period= 4.0 ns)
    Info: + Longest register to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
        Info: 2: + IC(0.200 ns) + CELL(2.000 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
        Info: Total cell delay = 2.000 ns ( 90.91 % )
        Info: Total interconnect delay = 0.200 ns ( 9.09 % )
    Info: - Smallest clock skew is 5.100 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 7.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_E30; Fanout = 3; REG Node = 'CURRENT_STATE.st3'
            Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.100 ns; Loc. = LC4_E30; Fanout = 1; COMB Node = 'Selector3~3'
            Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.000 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
            Info: Total cell delay = 5.200 ns ( 74.29 % )
            Info: Total interconnect delay = 1.800 ns ( 25.71 % )
        Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 3.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "CLK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "CURRENT_STATE.st4" and destination pin or register "F$latch" for clock "CLK" (Hold time is 1.9 ns)
    Info: + Largest clock skew is 5.200 ns
        Info: + Longest clock path from clock "CLK" to destination register is 7.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
            Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC4_E30; Fanout = 1; COMB Node = 'Selector3~3'
            Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
            Info: Total cell delay = 5.300 ns ( 74.65 % )
            Info: Total interconnect delay = 1.800 ns ( 25.35 % )
        Info: - Shortest clock path from clock "CLK" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: - Micro clock to output delay of source is 1.100 ns
    Info: - Shortest register to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
        Info: 2: + IC(0.200 ns) + CELL(2.000 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
        Info: Total cell delay = 2.000 ns ( 90.91 % )
        Info: Total interconnect delay = 0.200 ns ( 9.09 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tsu for register "CURRENT_STATE.st2" (data pin = "DaIN", clock pin = "CLK") is 2.500 ns
    Info: + Longest pin to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 5; CLK Node = 'DaIN'
        Info: 2: + IC(1.900 ns) + CELL(1.300 ns) = 3.700 ns; Loc. = LC5_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'
        Info: Total cell delay = 1.800 ns ( 48.65 % )
        Info: Total interconnect delay = 1.900 ns ( 51.35 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "CLK" to destination pin "F" through register "F$latch" is 17.300 ns
    Info: + Longest clock path from clock "CLK" to source register is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
        Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC4_E30; Fanout = 1; COMB Node = 'Selector3~3'
        Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
        Info: Total cell delay = 5.300 ns ( 74.65 % )
        Info: Total interconnect delay = 1.800 ns ( 25.35 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E30; Fanout = 1; REG Node = 'F$latch'
        Info: 2: + IC(1.700 ns) + CELL(8.500 ns) = 10.200 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'F'
        Info: Total cell delay = 8.500 ns ( 83.33 % )
        Info: Total interconnect delay = 1.700 ns ( 16.67 % )
Info: th for register "CURRENT_STATE.st4" (data pin = "DaIN", clock pin = "CLK") is -0.800 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 5; CLK Node = 'DaIN'
        Info: 2: + IC(1.900 ns) + CELL(1.200 ns) = 3.600 ns; Loc. = LC2_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st4'
        Info: Total cell delay = 1.700 ns ( 47.22 % )
        Info: Total interconnect delay = 1.900 ns ( 52.78 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Wed Nov 14 09:28:21 2007
    Info: Elapsed time: 00:00:01