chk.map.rpt

本设计是一个序列检测器

+--------------------------------+------------+
; Total logic elements           ; 6          ;
; Total combinational functions  ; 6          ;
;     -- Total 4-input functions ; 0          ;
;     -- Total 3-input functions ; 3          ;
;     -- Total 2-input functions ; 3          ;
;     -- Total 1-input functions ; 0          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 4          ;
; I/O pins                       ; 4          ;
; Maximum fan-out node           ; DaIN       ;
; Maximum fan-out                ; 5          ;
; Total fan-out                  ; 24         ;
; Average fan-out                ; 2.40       ;
+--------------------------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |CHK                       ; 6 (6)       ; 4            ; 0           ; 4    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |CHK                ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |CHK|CURRENT_STATE                                                                                    ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; CURRENT_STATE.st4 ; CURRENT_STATE.st3 ; CURRENT_STATE.st2 ; CURRENT_STATE.st1 ; CURRENT_STATE.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; CURRENT_STATE.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; CURRENT_STATE.st1 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; CURRENT_STATE.st2 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; CURRENT_STATE.st3 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; CURRENT_STATE.st4 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; F$latch                                            ; Selector3           ; yes                    ;
; Number of user-specified and inferred latches = 1  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; CURRENT_STATE.st1                     ; Lost fanout        ;
; Total Number of Removed Registers = 1 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 14 09:27:53 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CHK -c CHK
Info: Found 2 design units, including 1 entities, in source file CHK.vhd
    Info: Found design unit 1: CHK-behav
    Info: Found entity 1: CHK
Info: Elaborating entity "CHK" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at CHK.vhd(21): inferring latch(es) for signal or variable "F", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "F" at CHK.vhd(21)
Info: State machine "|CHK|CURRENT_STATE" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|CHK|CURRENT_STATE"
Info: Encoding result for state machine "|CHK|CURRENT_STATE"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "CURRENT_STATE.st4"
        Info: Encoded state bit "CURRENT_STATE.st3"
        Info: Encoded state bit "CURRENT_STATE.st2"
        Info: Encoded state bit "CURRENT_STATE.st1"
        Info: Encoded state bit "CURRENT_STATE.st0"
    Info: State "|CHK|CURRENT_STATE.st0" uses code string "00000"
    Info: State "|CHK|CURRENT_STATE.st1" uses code string "00011"
    Info: State "|CHK|CURRENT_STATE.st2" uses code string "00101"
    Info: State "|CHK|CURRENT_STATE.st3" uses code string "01001"
    Info: State "|CHK|CURRENT_STATE.st4" uses code string "10001"
Warning: Latch F$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CURRENT_STATE.st4
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "CURRENT_STATE.st1" lost all its fanouts during netlist optimizations.
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Wed Nov 14 09:27:57 2007
    Info: Elapsed time: 00:00:04