jianche.map.rpt

本设计是一个序列检测器

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |JIANCHE                   ; 0 (0)       ; 0            ; 0           ; 4    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |JIANCHE            ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |JIANCHE|CHK:u2|CURRENT_STATE                                                                         ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; CURRENT_STATE.st4 ; CURRENT_STATE.st3 ; CURRENT_STATE.st2 ; CURRENT_STATE.st1 ; CURRENT_STATE.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; CURRENT_STATE.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; CURRENT_STATE.st1 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; CURRENT_STATE.st2 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; CURRENT_STATE.st3 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; CURRENT_STATE.st4 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                           ;
+---------------------------------------+--------------------------------------+
; Register name                         ; Reason for Removal                   ;
+---------------------------------------+--------------------------------------+
; u1/inst/sub/110                       ; Stuck at GND due to stuck port clear ;
; u1/inst/sub/99                        ; Stuck at GND due to stuck port clear ;
; u1/inst/sub/87                        ; Stuck at GND due to stuck port clear ;
; u1/inst/sub/9                         ; Stuck at GND due to stuck port clear ;
; u2/CURRENT_STATE.st0                  ; Lost fanout                          ;
; u2/CURRENT_STATE.st1                  ; Lost fanout                          ;
; u2/CURRENT_STATE.st2                  ; Lost fanout                          ;
; u2/CURRENT_STATE.st3                  ; Lost fanout                          ;
; u2/CURRENT_STATE.st4                  ; Lost fanout                          ;
; Total Number of Removed Registers = 9 ;                                      ;
+---------------------------------------+--------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: xulie5:u1|74161:inst ;
+------------------------+--------+---------------------------------+
; Parameter Name         ; Value  ; Type                            ;
+------------------------+--------+---------------------------------+
; DEVICE_FAMILY          ; ACEX1K ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON     ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF    ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON     ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF    ; IGNORE_CASCADE                  ;
+------------------------+--------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Nov 27 14:14:39 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JIANCHE -c JIANCHE
Info: Found 1 design units, including 1 entities, in source file ../xulie5/xulie5.bdf
    Info: Found entity 1: xulie5
Info: Found 2 design units, including 1 entities, in source file JIANCHE.vhd
    Info: Found design unit 1: JIANCHE-behav
    Info: Found entity 1: JIANCHE
Info: Found 2 design units, including 1 entities, in source file CHK.vhd
    Info: Found design unit 1: CHK-behav
    Info: Found entity 1: CHK
Info: Elaborating entity "JIANCHE" for the top level hierarchy
Info: Elaborating entity "xulie5" for hierarchy "xulie5:u1"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus7.1/quartus/libraries/others/maxplus2/74161.tdf
    Info: Found entity 1: 74161
Info: Elaborating entity "74161" for hierarchy "xulie5:u1|74161:inst"
Info: Elaborated megafunction instantiation "xulie5:u1|74161:inst"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf
    Info: Found entity 1: f74161
Info: Elaborating entity "f74161" for hierarchy "xulie5:u1|74161:inst|f74161:sub"
Info: Elaborated megafunction instantiation "xulie5:u1|74161:inst|f74161:sub", which is child of megafunction instantiation "xulie5:u1|74161:inst"
Info: Elaborating entity "CHK" for hierarchy "CHK:u2"
Warning: Reduced register "xulie5:u1|74161:inst|f74161:sub|110" with stuck clear port to stuck value GND
Warning: Reduced register "xulie5:u1|74161:inst|f74161:sub|99" with stuck clear port to stuck value GND
Warning: Reduced register "xulie5:u1|74161:inst|f74161:sub|87" with stuck clear port to stuck value GND
Warning: Reduced register "xulie5:u1|74161:inst|f74161:sub|9" with stuck clear port to stuck value GND
Info: State machine "|JIANCHE|CHK:u2|CURRENT_STATE" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|JIANCHE|CHK:u2|CURRENT_STATE"
Info: Encoding result for state machine "|JIANCHE|CHK:u2|CURRENT_STATE"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "CHK:u2|CURRENT_STATE.st4"
        Info: Encoded state bit "CHK:u2|CURRENT_STATE.st3"
        Info: Encoded state bit "CHK:u2|CURRENT_STATE.st2"
        Info: Encoded state bit "CHK:u2|CURRENT_STATE.st1"
        Info: Encoded state bit "CHK:u2|CURRENT_STATE.st0"
    Info: State "|JIANCHE|CHK:u2|CURRENT_STATE.st0" uses code string "00000"
    Info: State "|JIANCHE|CHK:u2|CURRENT_STATE.st1" uses code string "00011"
    Info: State "|JIANCHE|CHK:u2|CURRENT_STATE.st2" uses code string "00101"
    Info: State "|JIANCHE|CHK:u2|CURRENT_STATE.st3" uses code string "01001"
    Info: State "|JIANCHE|CHK:u2|CURRENT_STATE.st4" uses code string "10001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "CQ" stuck at GND
    Warning: Pin "CO" stuck at GND
Info: 5 registers lost all their fanouts during netlist optimizations. The first 5 are displayed below.
    Info: Register "u2/CURRENT_STATE.st0" lost all its fanouts during netlist optimizations.
    Info: Register "u2/CURRENT_STATE.st1" lost all its fanouts during netlist optimizations.
    Info: Register "u2/CURRENT_STATE.st2" lost all its fanouts during netlist optimizations.
    Info: Register "u2/CURRENT_STATE.st3" lost all its fanouts during netlist optimizations.
    Info: Register "u2/CURRENT_STATE.st4" lost all its fanouts during netlist optimizations.
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clk"
    Warning: No output dependent on input pin "clr"
Info: Implemented 4 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 2 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Allocated 148 megabytes of memory during processing
    Info: Processing ended: Tue Nov 27 14:14:42 2007
    Info: Elapsed time: 00:00:03