prev_cmp_jianche.map.qmsg

本设计是一个序列检测器

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CHK CHK:u2 " "Info: Elaborating entity \"CHK\" for hierarchy \"CHK:u2\"" {  } { { "JIANCHE.vhd" "u2" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "xulie5:u1\|74161:inst\|f74161:sub\|110 clear GND " "Warning: Reduced register \"xulie5:u1\|74161:inst\|f74161:sub\|110\" with stuck clear port to stuck value GND" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "xulie5:u1\|74161:inst\|f74161:sub\|99 clear GND " "Warning: Reduced register \"xulie5:u1\|74161:inst\|f74161:sub\|99\" with stuck clear port to stuck value GND" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "xulie5:u1\|74161:inst\|f74161:sub\|87 clear GND " "Warning: Reduced register \"xulie5:u1\|74161:inst\|f74161:sub\|87\" with stuck clear port to stuck value GND" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 336 640 704 416 "87" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "xulie5:u1\|74161:inst\|f74161:sub\|9 clear GND " "Warning: Reduced register \"xulie5:u1\|74161:inst\|f74161:sub\|9\" with stuck clear port to stuck value GND" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 128 640 704 208 "9" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|JIANCHE\|CHK:u2\|CURRENT_STATE 5 " "Info: State machine \"\|JIANCHE\|CHK:u2\|CURRENT_STATE\" contains 5 states" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|JIANCHE\|CHK:u2\|CURRENT_STATE " "Info: Selected Auto state machine encoding method for state machine \"\|JIANCHE\|CHK:u2\|CURRENT_STATE\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|JIANCHE\|CHK:u2\|CURRENT_STATE " "Info: Encoding result for state machine \"\|JIANCHE\|CHK:u2\|CURRENT_STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "CHK:u2\|CURRENT_STATE.st4 " "Info: Encoded state bit \"CHK:u2\|CURRENT_STATE.st4\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "CHK:u2\|CURRENT_STATE.st3 " "Info: Encoded state bit \"CHK:u2\|CURRENT_STATE.st3\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "CHK:u2\|CURRENT_STATE.st2 " "Info: Encoded state bit \"CHK:u2\|CURRENT_STATE.st2\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "CHK:u2\|CURRENT_STATE.st1 " "Info: Encoded state bit \"CHK:u2\|CURRENT_STATE.st1\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "CHK:u2\|CURRENT_STATE.st0 " "Info: Encoded state bit \"CHK:u2\|CURRENT_STATE.st0\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|JIANCHE\|CHK:u2\|CURRENT_STATE.st0 00000 " "Info: State \"\|JIANCHE\|CHK:u2\|CURRENT_STATE.st0\" uses code string \"00000\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|JIANCHE\|CHK:u2\|CURRENT_STATE.st1 00011 " "Info: State \"\|JIANCHE\|CHK:u2\|CURRENT_STATE.st1\" uses code string \"00011\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|JIANCHE\|CHK:u2\|CURRENT_STATE.st2 00101 " "Info: State \"\|JIANCHE\|CHK:u2\|CURRENT_STATE.st2\" uses code string \"00101\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|JIANCHE\|CHK:u2\|CURRENT_STATE.st3 01001 " "Info: State \"\|JIANCHE\|CHK:u2\|CURRENT_STATE.st3\" uses code string \"01001\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|JIANCHE\|CHK:u2\|CURRENT_STATE.st4 10001 " "Info: State \"\|JIANCHE\|CHK:u2\|CURRENT_STATE.st4\" uses code string \"10001\"" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "CQ GND " "Warning: Pin \"CQ\" stuck at GND" {  } { { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "CO GND " "Warning: Pin \"CO\" stuck at GND" {  } { { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "5 5 " "Info: 5 registers lost all their fanouts during netlist optimizations. The first 5 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u2/CURRENT_STATE.st0 " "Info: Register \"u2/CURRENT_STATE.st0\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u2/CURRENT_STATE.st1 " "Info: Register \"u2/CURRENT_STATE.st1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u2/CURRENT_STATE.st2 " "Info: Register \"u2/CURRENT_STATE.st2\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u2/CURRENT_STATE.st3 " "Info: Register \"u2/CURRENT_STATE.st3\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u2/CURRENT_STATE.st4 " "Info: Register \"u2/CURRENT_STATE.st4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk " "Warning: No output dependent on input pin \"clk\"" {  } { { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clr " "Warning: No output dependent on input pin \"clr\"" {  } { { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Info: Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 14:14:42 2007 " "Info: Processing ended: Tue Nov 27 14:14:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}