prev_cmp_jianche.qmsg

本设计是一个序列检测器

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 10:15:46 2007 " "Info: Processing ended: Wed Nov 21 10:15:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 10:15:47 2007 " "Info: Processing started: Wed Nov 21 10:15:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off JIANCHE -c JIANCHE " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off JIANCHE -c JIANCHE" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 10:15:53 2007 " "Info: Processing ended: Wed Nov 21 10:15:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 10:15:55 2007 " "Info: Processing started: Wed Nov 21 10:15:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off JIANCHE -c JIANCHE " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off JIANCHE -c JIANCHE" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register xulie5:u1\|74161:inst\|f74161:sub\|99 register CHK:u2\|CURRENT_STATE.st4 158.73 MHz 6.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 158.73 MHz between source register \"xulie5:u1\|74161:inst\|f74161:sub\|99\" and destination register \"CHK:u2\|CURRENT_STATE.st4\" (period= 6.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulie5:u1\|74161:inst\|f74161:sub\|99 1 REG LC7_C9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C9; Fanout = 4; REG Node = 'xulie5:u1\|74161:inst\|f74161:sub\|99'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns xulie5:u1\|inst16~140 2 COMB LC1_C9 6 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC1_C9; Fanout = 6; COMB Node = 'xulie5:u1\|inst16~140'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 } "NODE_NAME" } } { "../xulie5/xulie5.bdf" "" { Schematic "E:/学习/作业/eda作业/JIANCHE/xulie5/xulie5.bdf" { { 320 1192 1296 432 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.000 ns) 4.500 ns CHK:u2\|CURRENT_STATE.st4 3 REG LC1_C6 1 " "Info: 3: + IC(1.100 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC1_C6; Fanout = 1; REG Node = 'CHK:u2\|CURRENT_STATE.st4'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { xulie5:u1|inst16~140 CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 71.11 % ) " "Info: Total cell delay = 3.200 ns ( 71.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 28.89 % ) " "Info: Total interconnect delay = 1.300 ns ( 28.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|CURRENT_STATE.st4 } { 0.000ns 0.200ns 1.100ns } { 0.000ns 2.200ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns CHK:u2\|CURRENT_STATE.st4 2 REG LC1_C6 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_C6; Fanout = 1; REG Node = 'CHK:u2\|CURRENT_STATE.st4'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out CHK:u2|CURRENT_STATE.st4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns xulie5:u1\|74161:inst\|f74161:sub\|99 2 REG LC7_C9 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_C9; Fanout = 4; REG Node = 'xulie5:u1\|74161:inst\|f74161:sub\|99'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out xulie5:u1|74161:inst|f74161:sub|99 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out CHK:u2|CURRENT_STATE.st4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out xulie5:u1|74161:inst|f74161:sub|99 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|CURRENT_STATE.st4 } { 0.000ns 0.200ns 1.100ns } { 0.000ns 2.200ns 1.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk CHK:u2|CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out CHK:u2|CURRENT_STATE.st4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out xulie5:u1|74161:inst|f74161:sub|99 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk CO xulie5:u1\|74161:inst\|f74161:sub\|99 17.500 ns register " "Info: tco from clock \"clk\" to destination pin \"CO\" through register \"xulie5:u1\|74161:inst\|f74161:sub\|99\" is 17.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns xulie5:u1\|74161:inst\|f74161:sub\|99 2 REG LC7_C9 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_C9; Fanout = 4; REG Node = 'xulie5:u1\|74161:inst\|f74161:sub\|99'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out xulie5:u1|74161:inst|f74161:sub|99 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest register pin " "Info: + Longest register to pin delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulie5:u1\|74161:inst\|f74161:sub\|99 1 REG LC7_C9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C9; Fanout = 4; REG Node = 'xulie5:u1\|74161:inst\|f74161:sub\|99'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 544 640 704 624 "99" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns xulie5:u1\|inst16~140 2 COMB LC1_C9 6 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC1_C9; Fanout = 6; COMB Node = 'xulie5:u1\|inst16~140'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 } "NODE_NAME" } } { "../xulie5/xulie5.bdf" "" { Schematic "E:/学习/作业/eda作业/JIANCHE/xulie5/xulie5.bdf" { { 320 1192 1296 432 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 5.200 ns CHK:u2\|F~28 3 COMB LC8_C6 1 " "Info: 3: + IC(1.100 ns) + CELL(1.700 ns) = 5.200 ns; Loc. = LC8_C6; Fanout = 1; COMB Node = 'CHK:u2\|F~28'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { xulie5:u1|inst16~140 CHK:u2|F~28 } "NODE_NAME" } } { "CHK.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/CHK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(8.600 ns) 14.500 ns CO 4 PIN PIN_136 0 " "Info: 4: + IC(0.700 ns) + CELL(8.600 ns) = 14.500 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'CO'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { CHK:u2|F~28 CO } "NODE_NAME" } } { "JIANCHE.vhd" "" { Text "E:/学习/作业/eda作业/JIANCHE/JIANCHE/JIANCHE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns ( 86.21 % ) " "Info: Total cell delay = 12.500 ns ( 86.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 13.79 % ) " "Info: Total interconnect delay = 2.000 ns ( 13.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|F~28 CO } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|F~28 CO } { 0.000ns 0.200ns 1.100ns 0.700ns } { 0.000ns 2.200ns 1.700ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk xulie5:u1|74161:inst|f74161:sub|99 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out xulie5:u1|74161:inst|f74161:sub|99 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|F~28 CO } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { xulie5:u1|74161:inst|f74161:sub|99 xulie5:u1|inst16~140 CHK:u2|F~28 CO } { 0.000ns 0.200ns 1.100ns 0.700ns } { 0.000ns 2.200ns 1.700ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 10:15:56 2007 " "Info: Processing ended: Wed Nov 21 10:15:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1  " "Info: Quartus II Full Compilation was successful. 0 errors, 1 warning" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}