freqtest.vhd

VHDL编写的数字显示型频率测试仪

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST  IS
  PORT (CLK:IN STD_LOGIC;
        FSIN:IN STD_LOGIC;
        DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ;
ARCHITECTURE struc OF FREQTEST IS
   COMPONENT TESTCTL
PORT(CLK:IN  STD_LOGIC;
     TSTEN:OUT STD_LOGIC;
     CLR_CNT:OUT STD_LOGIC;
     LOAD:OUT STD_LOGIC );
END COMPONENT;
COMPONENT CNT10
 PORT(CLK:IN STD_LOGIC;CLR:IN STD_LOGIC;ENA:IN STD_LOGIC;
     CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      CARRY_OUT: OUT STD_LOGIC );
 END COMPONENT;
COMPONENT REG32B
PORT (LOAD:IN STD_LOGIC;
      DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT;
SIGNAL LOAD1,TSTEN1,CLR_CNT1:STD_LOGIC;
SIGNAL DTO1:STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CARRY_OUT1:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
U1:TESTCTL PORT MAP(CLK=>CLK, TSTEN=>TSTEN1,
                    CLR_CNT=>CLR_CNT1,LOAD=>LOAD1);
U2:REG32B PORT MAP(LOAD=>LOAD1,DIN=>DTO1,DOUT=>DOUT);
U3:CNT10 PORT MAP(CLK=>FSIN,CLR=>CLR_CNT1,ENA=>TSTEN1,
               CQ=>DTO1(3 DOWNTO 0),CARRY_OUT=>CARRY_OUT1(0));
U4:CNT10 PORT MAP(CLK=>CARRY_OUT1(0),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(7 DOWNTO 4),
                   CARRY_OUT=>CARRY_OUT1(1));
U5:CNT10 PORT MAP(CLK=>CARRY_OUT1(1),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(11 DOWNTO 8),
                   CARRY_OUT=>CARRY_OUT1(2));
U6:CNT10 PORT MAP(CLK=>CARRY_OUT1(2),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(15 DOWNTO 12),
                   CARRY_OUT=>CARRY_OUT1(3));
U7:CNT10 PORT MAP(CLK=>CARRY_OUT1(3),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(19 DOWNTO 16),
                   CARRY_OUT=>CARRY_OUT1(4));
U8:CNT10 PORT MAP(CLK=>CARRY_OUT1(4),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(23 DOWNTO 20),
                   CARRY_OUT=>CARRY_OUT1(5));
U9:CNT10 PORT MAP(CLK=>CARRY_OUT1(5),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(27 DOWNTO 24),
                   CARRY_OUT=>CARRY_OUT1(6));
U10:CNT10 PORT MAP(CLK=>CARRY_OUT1(6),CLR=>CLR_CNT1,
                   ENA=>TSTEN1,CQ=>DTO1(31 DOWNTO 28));
END struc;