ad0804.tan.qmsg

来自「对ad0804的控制工程」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode register sld_hub:sld_hub_inst\|hub_tdo_reg 83.75 MHz 11.94 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 83.75 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 11.94 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.707 ns + Longest register register " "Info: + Longest register to register delay is 5.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode 1 REG LCFF_X16_Y12_N15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y12_N15; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.624 ns) 1.053 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LCCOMB_X16_Y12_N26 6 " "Info: 2: + IC(0.429 ns) + CELL(0.624 ns) = 1.053 ns; Loc. = LCCOMB_X16_Y12_N26; Fanout = 6; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.053 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.206 ns) 2.304 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 3 COMB LCCOMB_X17_Y12_N28 4 " "Info: 3: + IC(1.045 ns) + CELL(0.206 ns) = 2.304 ns; Loc. = LCCOMB_X17_Y12_N28; Fanout = 4; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.251 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 803 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.206 ns) 2.890 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55 4 COMB LCCOMB_X17_Y12_N22 18 " "Info: 4: + IC(0.380 ns) + CELL(0.206 ns) = 2.890 ns; Loc. = LCCOMB_X17_Y12_N22; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.586 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.206 ns) 3.464 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 5 COMB LCCOMB_X17_Y12_N30 1 " "Info: 5: + IC(0.368 ns) + CELL(0.206 ns) = 3.464 ns; Loc. = LCCOMB_X17_Y12_N30; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.574 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.624 ns) 4.465 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 6 COMB LCCOMB_X17_Y12_N6 1 " "Info: 6: + IC(0.377 ns) + CELL(0.624 ns) = 4.465 ns; Loc. = LCCOMB_X17_Y12_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.001 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.206 ns) 5.035 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LCCOMB_X17_Y12_N2 1 " "Info: 7: + IC(0.364 ns) + CELL(0.206 ns) = 5.035 ns; Loc. = LCCOMB_X17_Y12_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.206 ns) 5.599 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LCCOMB_X17_Y12_N0 1 " "Info: 8: + IC(0.358 ns) + CELL(0.206 ns) = 5.599 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.707 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LCFF_X17_Y12_N1 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 5.707 ns; Loc. = LCFF_X17_Y12_N1; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.386 ns ( 41.81 % ) " "Info: Total cell delay = 2.386 ns ( 41.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.321 ns ( 58.19 % ) " "Info: Total interconnect delay = 3.321 ns ( 58.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.707 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.707 ns" { sld_hub:sld_hub_inst|jtag_debug_mode {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.429ns 1.045ns 0.380ns 0.368ns 0.377ns 0.364ns 0.358ns 0.000ns } { 0.000ns 0.624ns 0.206ns 0.206ns 0.206ns 0.624ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.404 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.831 ns) + CELL(0.000 ns) 3.831 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 451 " "Info: 2: + IC(3.831 ns) + CELL(0.000 ns) = 3.831 ns; Loc. = CLKCTRL_G3; Fanout = 451; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.831 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 5.404 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X17_Y12_N1 2 " "Info: 3: + IC(0.907 ns) + CELL(0.666 ns) = 5.404 ns; Loc. = LCFF_X17_Y12_N1; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.32 % ) " "Info: Total cell delay = 0.666 ns ( 12.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.738 ns ( 87.68 % ) " "Info: Total interconnect delay = 4.738 ns ( 87.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.404 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.404 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.831ns 0.907ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.403 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.403 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.831 ns) + CELL(0.000 ns) 3.831 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 451 " "Info: 2: + IC(3.831 ns) + CELL(0.000 ns) = 3.831 ns; Loc. = CLKCTRL_G3; Fanout = 451; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.831 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 5.403 ns sld_hub:sld_hub_inst\|jtag_debug_mode 3 REG LCFF_X16_Y12_N15 2 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 5.403 ns; Loc. = LCFF_X16_Y12_N15; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.33 % ) " "Info: Total cell delay = 0.666 ns ( 12.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.737 ns ( 87.67 % ) " "Info: Total interconnect delay = 4.737 ns ( 87.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.403 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.403 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.831ns 0.906ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.404 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.404 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.831ns 0.907ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.403 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.403 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.831ns 0.906ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.707 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.707 ns" { sld_hub:sld_hub_inst|jtag_debug_mode {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.429ns 1.045ns 0.380ns 0.368ns 0.377ns 0.364ns 0.358ns 0.000ns } { 0.000ns 0.624ns 0.206ns 0.206ns 0.206ns 0.624ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.404 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.404 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.831ns 0.907ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.403 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.403 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.831ns 0.906ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] d5 clk 6.228 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]\" (data pin = \"d5\", clock pin = \"clk\") is 6.228 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.085 ns + Longest pin register " "Info: + Longest pin to register delay is 9.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns d5 1 PIN PIN_44 3 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_44; Fanout = 3; PIN Node = 'd5'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d5 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.630 ns) + CELL(0.460 ns) 9.085 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] 2 REG LCFF_X26_Y10_N9 3 " "Info: 2: + IC(7.630 ns) + CELL(0.460 ns) = 9.085 ns; Loc. = LCFF_X26_Y10_N9; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "8.090 ns" { d5 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.455 ns ( 16.02 % ) " "Info: Total cell delay = 1.455 ns ( 16.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.630 ns ( 83.98 % ) " "Info: Total interconnect delay = 7.630 ns ( 83.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "9.085 ns" { d5 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "9.085 ns" { d5 {} d5~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] {} } { 0.000ns 0.000ns 7.630ns } { 0.000ns 0.995ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.817 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 465 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 465; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.872 ns) + CELL(0.666 ns) 2.817 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] 3 REG LCFF_X26_Y10_N9 3 " "Info: 3: + IC(0.872 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X26_Y10_N9; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.538 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.11 % ) " "Info: Total cell delay = 1.806 ns ( 64.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.011 ns ( 35.89 % ) " "Info: Total interconnect delay = 1.011 ns ( 35.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.817 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] {} } { 0.000ns 0.000ns 0.139ns 0.872ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "9.085 ns" { d5 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "9.085 ns" { d5 {} d5~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] {} } { 0.000ns 0.000ns 7.630ns } { 0.000ns 0.995ns 0.460ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.817 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] {} } { 0.000ns 0.000ns 0.139ns 0.872ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}