ad0804.tan.qmsg

来自「对ad0804的控制工程」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk START START~reg0 9.680 ns register " "Info: tco from clock \"clk\" to destination pin \"START\" through register \"START~reg0\" is 9.680 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.850 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 465 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 465; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 2.850 ns START~reg0 3 REG LCFF_X22_Y6_N19 4 " "Info: 3: + IC(0.905 ns) + CELL(0.666 ns) = 2.850 ns; Loc. = LCFF_X22_Y6_N19; Fanout = 4; REG Node = 'START~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { clk~clkctrl START~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.37 % ) " "Info: Total cell delay = 1.806 ns ( 63.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.044 ns ( 36.63 % ) " "Info: Total interconnect delay = 1.044 ns ( 36.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { clk clk~clkctrl START~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { clk {} clk~combout {} clk~clkctrl {} START~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.526 ns + Longest register pin " "Info: + Longest register to pin delay is 6.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns START~reg0 1 REG LCFF_X22_Y6_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y6_N19; Fanout = 4; REG Node = 'START~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { START~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.230 ns) + CELL(3.296 ns) 6.526 ns START 2 PIN PIN_58 0 " "Info: 2: + IC(3.230 ns) + CELL(3.296 ns) = 6.526 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'START'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.526 ns" { START~reg0 START } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.296 ns ( 50.51 % ) " "Info: Total cell delay = 3.296 ns ( 50.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.230 ns ( 49.49 % ) " "Info: Total interconnect delay = 3.230 ns ( 49.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.526 ns" { START~reg0 START } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.526 ns" { START~reg0 {} START {} } { 0.000ns 3.230ns } { 0.000ns 3.296ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { clk clk~clkctrl START~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { clk {} clk~combout {} clk~clkctrl {} START~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.526 ns" { START~reg0 START } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.526 ns" { START~reg0 {} START {} } { 0.000ns 3.230ns } { 0.000ns 3.296ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rst_n altera_auto_signaltap_0_rst_n_ae 4.045 ns Longest " "Info: Longest tpd from source pin \"rst_n\" to destination pin \"altera_auto_signaltap_0_rst_n_ae\" is 4.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns rst_n 1 PIN PIN_129 9 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_129; Fanout = 9; PIN Node = 'rst_n'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.561 ns) + CELL(0.319 ns) 3.030 ns altera_auto_signaltap_0_rst_n_signaltap_lcell 2 COMB LCCOMB_X22_Y6_N4 1 " "Info: 2: + IC(1.561 ns) + CELL(0.319 ns) = 3.030 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_rst_n_signaltap_lcell'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { rst_n altera_auto_signaltap_0_rst_n_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.000 ns) 4.045 ns altera_auto_signaltap_0_rst_n_ae 3 PIN LCCOMB_X18_Y6_N0 0 " "Info: 3: + IC(1.015 ns) + CELL(0.000 ns) = 4.045 ns; Loc. = LCCOMB_X18_Y6_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_rst_n_ae'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" {