prev_cmp_ad0804.tan.qmsg

来自「对ad0804的控制工程」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "scl~reg0 " "Info: Detected ripple clock \"scl~reg0\" as buffer" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 29 0 0 } } { "e:/altera/c72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/c72/quartus/bin/Assignment Editor.qase" 1 { { 0 "scl~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register NS.GET_DATA register led1~reg0 227.69 MHz 4.392 ns Internal " "Info: Clock \"clk\" has Internal fmax of 227.69 MHz between source register \"NS.GET_DATA\" and destination register \"led1~reg0\" (period= 4.392 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.950 ns + Longest register register " "Info: + Longest register to register delay is 1.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NS.GET_DATA 1 REG LCFF_X8_Y3_N9 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y3_N9; Fanout = 12; REG Node = 'NS.GET_DATA'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { NS.GET_DATA } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.319 ns) 0.768 ns led1~0 2 COMB LCCOMB_X8_Y3_N6 8 " "Info: 2: + IC(0.449 ns) + CELL(0.319 ns) = 0.768 ns; Loc. = LCCOMB_X8_Y3_N6; Fanout = 8; COMB Node = 'led1~0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.768 ns" { NS.GET_DATA led1~0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.855 ns) 1.950 ns led1~reg0 3 REG LCFF_X8_Y3_N3 1 " "Info: 3: + IC(0.327 ns) + CELL(0.855 ns) = 1.950 ns; Loc. = LCFF_X8_Y3_N3; Fanout = 1; REG Node = 'led1~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.182 ns" { led1~0 led1~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.174 ns ( 60.21 % ) " "Info: Total cell delay = 1.174 ns ( 60.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.776 ns ( 39.79 % ) " "Info: Total interconnect delay = 0.776 ns ( 39.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.950 ns" { NS.GET_DATA led1~0 led1~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "1.950 ns" { NS.GET_DATA {} led1~0 {} led1~reg0 {} } { 0.000ns 0.449ns 0.327ns } { 0.000ns 0.319ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.178 ns - Smallest " "Info: - Smallest clock skew is -2.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.870 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.666 ns) 2.870 ns led1~reg0 3 REG LCFF_X8_Y3_N3 1 " "Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X8_Y3_N3; Fanout = 1; REG Node = 'led1~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { clk~clkctrl led1~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.93 % ) " "Info: Total cell delay = 1.806 ns ( 62.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 37.07 % ) " "Info: Total interconnect delay = 1.064 ns ( 37.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { clk clk~clkctrl led1~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { clk {} clk~combout {} clk~clkctrl {} led1~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.048 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns scl~reg0 2 REG LCFF_X1_Y9_N31 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N31; Fanout = 3; REG Node = 'scl~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk scl~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.000 ns) 3.457 ns scl~reg0clkctrl 3 COMB CLKCTRL_G1 10 " "Info: 3: + IC(0.825 ns) + CELL(0.000 ns) = 3.457 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'scl~reg0clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { scl~reg0 scl~reg0clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.666 ns) 5.048 ns NS.GET_DATA 4 REG LCFF_X8_Y3_N9 12 " "Info: 4: + IC(0.925 ns) + CELL(0.666 ns) = 5.048 ns; Loc. = LCFF_X8_Y3_N9; Fanout = 12; REG Node = 'NS.GET_DATA'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { scl~reg0clkctrl NS.GET_DATA } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 54.99 % ) " "Info: Total cell delay = 2.776 ns ( 54.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.272 ns ( 45.01 % ) " "Info: Total interconnect delay = 2.272 ns ( 45.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.048 ns" { clk scl~reg0 scl~reg0clkctrl NS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.048 ns" { clk {} clk~combout {} scl~reg0 {} scl~reg0clkctrl {} NS.GET_DATA {} } { 0.000ns 0.000ns 0.522ns 0.825ns 0.925ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { clk clk~clkctrl led1~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { clk {} clk~combout {} clk~clkctrl {} led1~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.048 ns" { clk scl~reg0 scl~reg0clkctrl NS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.048 ns" { clk {} clk~combout {} scl~reg0 {} scl~reg0clkctrl {} NS.GET_DATA {} } { 0.000ns 0.000ns 0.522ns 0.825ns 0.925ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.950 ns" { NS.GET_DATA led1~0 led1~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "1.950 ns" { NS.GET_DATA {} led1~0 {} led1~reg0 {} } { 0.000ns 0.449ns 0.327ns } { 0.000ns 0.319ns 0.855ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { clk clk~clkctrl led1~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { clk {} clk~combout {} clk~clkctrl {} led1~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.048 ns" { clk scl~reg0 scl~reg0clkctrl NS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.048 ns" { clk {} clk~combout {} scl~reg0 {} scl~reg0clkctrl {} NS.GET_DATA {} } { 0.000ns 0.000ns 0.522ns 0.825ns 0.925ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "s1 d1 clk 4.694 ns register " "Info: tsu for register \"s1\" (data pin = \"d1\", clock pin = \"clk\") is 4.694 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.603 ns + Longest pin register " "Info: + Longest pin to register delay is 7.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.965 ns) 0.965 ns d1 1 PIN PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(0.965 ns) = 0.965 ns; Loc. = PIN_39; Fanout = 1; PIN Node = 'd1'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d1 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.178 ns) + CELL(0.460 ns) 7.603 ns s1 2 REG LCFF_X7_Y3_N23 1 " "Info: 2: + IC(6.178 ns) + CELL(0.460 ns) = 7.603 ns; Loc. = LCFF_X7_Y3_N23; Fanout = 1; REG Node = 's1'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.638 ns" { d1 s1 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.425 ns ( 18.74 % ) " "Info: Total cell delay = 1.425 ns ( 18.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.178 ns ( 81.26 % ) " "Info: Total interconnect delay = 6.178 ns ( 81.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "7.603 ns" { d1 s1 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "7.603 ns" { d1 {} d1~combout {} s1 {} } { 0.000ns 0.000ns 6.178ns } { 0.000ns 0.965ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.869 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.666 ns) 2.869 ns s1 3 REG LCFF_X7_Y3_N23 1 " "Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.869 ns; Loc. = LCFF_X7_Y3_N23; Fanout = 1; REG Node = 's1'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { clk~clkctrl s1 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.95 % ) " "Info: Total cell delay = 1.806 ns ( 62.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.063 ns ( 37.05 % ) " "Info: Total interconnect delay = 1.063 ns ( 37.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.869 ns" { clk clk~clkctrl s1 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.869 ns" { clk {} clk~combout {} clk~clkctrl {} s1 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "7.603 ns" { d1 s1 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "7.603 ns" { d1 {} d1~combout {} s1 {} } { 0.000ns 0.000ns 6.178ns } { 0.000ns 0.965ns 0.460ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.869 ns" { clk clk~clkctrl s1 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.869 ns" { clk {} clk~combout {} clk~clkctrl {} s1 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led8 led8~reg0 9.260 ns register " "Info: tco from clock \"clk\" to destination pin \"led8\" through register \"led8~reg0\" is 9.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.870 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.666 ns) 2.870 ns led8~reg0 3 REG LCFF_X8_Y3_N13 1 " "Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X8_Y3_N13; Fanout = 1; REG Node = 'led8~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { clk~clkctrl led8~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.93 % ) " "Info: Total cell delay = 1.806 ns ( 62.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 37.07 % ) " "Info: Total interconnect delay = 1.064 ns ( 37.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { clk clk~clkctrl led8~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { clk {} clk~combout {} clk~clkctrl {} led8~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.086 ns + Longest register pin " "Info: + Longest register to pin delay is 6.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led8~reg0 1 REG LCFF_X8_Y3_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y3_N13; Fanout = 1; REG Node = 'led8~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led8~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.820 ns) + CELL(3.266 ns) 6.086 ns led8 2 PIN PIN_88 0 " "Info: 2: + IC(2.820 ns) + CELL(3.266 ns) = 6.086 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'led8'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.086 ns" { led8~reg0 led8 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 53.66 % ) " "Info: Total cell delay = 3.266 ns ( 53.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.820 ns ( 46.34 % ) " "Info: Total interconnect delay = 2.820 ns ( 46.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.086 ns" { led8~reg0 led8 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.086 ns" { led8~reg0 {} led8 {} } { 0.000ns 2.820ns } { 0.000ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { clk clk~clkctrl led8~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { clk {} clk~combout {} clk~clkctrl {} led8~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.086 ns" { led8~reg0 led8 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.086 ns" { led8~reg0 {} led8 {} } { 0.000ns 2.820ns } { 0.000ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}