prev_cmp_ad0804.tan.qmsg

来自「对ad0804的控制工程」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "CS.GET_DATA rst_n clk 1.351 ns register " "Info: th for register \"CS.GET_DATA\" (data pin = \"rst_n\", clock pin = \"clk\") is 1.351 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.049 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns scl~reg0 2 REG LCFF_X1_Y9_N31 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N31; Fanout = 3; REG Node = 'scl~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk scl~reg0 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.000 ns) 3.457 ns scl~reg0clkctrl 3 COMB CLKCTRL_G1 10 " "Info: 3: + IC(0.825 ns) + CELL(0.000 ns) = 3.457 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'scl~reg0clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { scl~reg0 scl~reg0clkctrl } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.666 ns) 5.049 ns CS.GET_DATA 4 REG LCFF_X9_Y3_N31 1 " "Info: 4: + IC(0.926 ns) + CELL(0.666 ns) = 5.049 ns; Loc. = LCFF_X9_Y3_N31; Fanout = 1; REG Node = 'CS.GET_DATA'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { scl~reg0clkctrl CS.GET_DATA } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 54.98 % ) " "Info: Total cell delay = 2.776 ns ( 54.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.273 ns ( 45.02 % ) " "Info: Total interconnect delay = 2.273 ns ( 45.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.049 ns" { clk scl~reg0 scl~reg0clkctrl CS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.049 ns" { clk {} clk~combout {} scl~reg0 {} scl~reg0clkctrl {} CS.GET_DATA {} } { 0.000ns 0.000ns 0.522ns 0.825ns 0.926ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.004 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns rst_n 1 PIN PIN_129 6 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_129; Fanout = 6; PIN Node = 'rst_n'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.540 ns) + CELL(0.206 ns) 3.896 ns CS~67 2 COMB LCCOMB_X9_Y3_N30 1 " "Info: 2: + IC(2.540 ns) + CELL(0.206 ns) = 3.896 ns; Loc. = LCCOMB_X9_Y3_N30; Fanout = 1; COMB Node = 'CS~67'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.746 ns" { rst_n CS~67 } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.004 ns CS.GET_DATA 3 REG LCFF_X9_Y3_N31 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 4.004 ns; Loc. = LCFF_X9_Y3_N31; Fanout = 1; REG Node = 'CS.GET_DATA'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { CS~67 CS.GET_DATA } "NODE_NAME" } } { "ad0804.v" "" { Text "F:/72quartus/ADCONTRL0804/ad0804.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.464 ns ( 36.56 % ) " "Info: Total cell delay = 1.464 ns ( 36.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.540 ns ( 63.44 % ) " "Info: Total interconnect delay = 2.540 ns ( 63.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "4.004 ns" { rst_n CS~67 CS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "4.004 ns" { rst_n {} rst_n~combout {} CS~67 {} CS.GET_DATA {} } { 0.000ns 0.000ns 2.540ns 0.000ns } { 0.000ns 1.150ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.049 ns" { clk scl~reg0 scl~reg0clkctrl CS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.049 ns" { clk {} clk~combout {} scl~reg0 {} scl~reg0clkctrl {} CS.GET_DATA {} } { 0.000ns 0.000ns 0.522ns 0.825ns 0.926ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "4.004 ns" { rst_n CS~67 CS.GET_DATA } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "4.004 ns" { rst_n {} rst_n~combout {} CS~67 {} CS.GET_DATA {} } { 0.000ns 0.000ns 2.540ns 0.000ns } { 0.000ns 1.150ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 15 17:52:13 2008 " "Info: Processing ended: Wed Oct 15 17:52:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}