prev_cmp_1013.qmsg

用verilog写的对ad0809的控制

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Warning" "WOPT_OPT_NOT_GATE_PUSH_BACK_ENFORCED" "" "Warning: NOT_GATE_PUSH_BACK-forbidden assignments are ignored" { { "Warning" "WOPT_OPT_NOT_GATE_PUSH_BACK_ENFORCED_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] " "Warning: NOT_GATE_PUSH_BACK performed on sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\]" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "NOT_GATE_PUSH_BACK performed on %1!s!" 0 0 "" 0}  } {  } 0 0 "NOT_GATE_PUSH_BACK-forbidden assignments are ignored" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] will power up to High" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[5\] High " "Critical Warning: Register sld_signaltap:auto_si