serial.fit.eqn

串口通讯 verilog CPLD EPM1270 源代码

--operation mode is normal

div8_rec_reg[0]_lut_out = !div8_rec_reg[0];
div8_rec_reg[0] = DFFEAS(div8_rec_reg[0]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , recstart, , , , );


--A1L612 is rxd_buf[7]~143 at LC_X12_Y4_N0
--operation mode is normal

A1L612 = div8_rec_reg[0] & div8_rec_reg[2] & div8_rec_reg[1];


--state_rec[2] is state_rec[2] at LC_X13_Y4_N1
--operation mode is normal

state_rec[2]_lut_out = A1L142 & (state_rec[2]) # !A1L142 & !A1L542 & (state_rec[2] $ A1L61);
state_rec[2] = DFFEAS(state_rec[2]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--state_rec[1] is state_rec[1] at LC_X13_Y4_N8
--operation mode is normal

state_rec[1]_lut_out = A1L142 & state_rec[1] # !A1L142 & !A1L542 & (state_rec[1] $ state_rec[0]);
state_rec[1] = DFFEAS(state_rec[1]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--A1L451 is recstart~107 at LC_X12_Y4_N5
--operation mode is normal

A1L451 = !state_rec[1] & (!state_rec[2]);


--state_rec[0] is state_rec[0] at LC_X13_Y4_N7
--operation mode is normal

state_rec[0]_lut_out = state_rec[0] & (A1L142) # !state_rec[0] & !A1L542 & !A1L142;
state_rec[0] = DFFEAS(state_rec[0]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--state_rec[3] is state_rec[3] at LC_X13_Y4_N2
--operation mode is normal

state_rec[3]_lut_out = A1L142 & (state_rec[3]) # !A1L142 & !A1L542 & (state_rec[3] $ A1L71);
state_rec[3] = DFFEAS(state_rec[3]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--A1L712 is rxd_buf[7]~144 at LC_X12_Y4_N6
--operation mode is normal

A1L712 = A1L612 & (state_rec[3] $ (state_rec[0] # !A1L451));


--A1L432 is send_state[2]~96 at LC_X14_Y5_N7
--operation mode is normal

A1L432 = state_tras[1] & state_tras[3];


--A1L762 is txd_buf~1751 at LC_X14_Y5_N3
--operation mode is normal

A1L762 = A1L432 & (send_state[1] & !send_state[2] # !send_state[1] & (send_state[2] # !send_state[0]));


--txd_buf[1] is txd_buf[1] at LC_X14_Y4_N5
--operation mode is normal

txd_buf[1]_lut_out = A1L662 & txd_buf[2] # !A1L662 & (A1L962);
txd_buf[1] = DFFEAS(txd_buf[1]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , A1L162, VCC, , , !key_entry2);


--A1L862 is txd_buf~1752 at LC_X14_Y6_N1
--operation mode is normal

A1L862 = txd_buf[1] & (!state_tras[3] # !state_tras[1]) # !key_entry2;


--A1L952 is txd_buf[3]~1753 at LC_X14_Y6_N7
--operation mode is normal

A1L952 = state_tras[2] # !state_tras[0] # !state_tras[3];


--A1L062 is txd_buf[3]~1755 at LC_X14_Y6_N6
--operation mode is normal

A1L062 = state_tras[0] & state_tras[3] & (state_tras[2] $ state_tras[1]) # !state_tras[0] & (state_tras[3] $ (!state_tras[2] & !state_tras[1]));


--key_entry1 is key_entry1 at LC_X14_Y7_N2
--operation mode is normal

key_entry1_lut_out = key_entry1 # !key_input & (!A1L751);
key_entry1 = DFFEAS(key_entry1_lut_out, GLOBAL(clk), VCC, , , ~GND, , !rst, key_entry2);


--A1L162 is txd_buf[3]~1756 at LC_X14_Y6_N8
--operation mode is normal

A1L162 = key_entry2 & (!A1L062 & A1L951) # !key_entry2 & key_entry1;


--A1L29 is div8_tras_reg[2]~59 at LC_X15_Y5_N1
--operation mode is normal

A1L29 = trasstart & div8_tras_reg[1] & (div8_tras_reg[0]);


--A1L09 is div8_tras_reg[1]~60 at LC_X15_Y5_N2
--operation mode is normal

A1L09 = div8_tras_reg[0] & (trasstart);


--A1L6 is Select~2999 at LC_X15_Y4_N9
--operation mode is normal

A1L6 = !state_tras[0] & !state_tras[2] & !state_tras[3] & !state_tras[1];


--A1L7 is Select~3000 at LC_X14_Y4_N8
--operation mode is normal

A1L7 = trasstart # !send_state[2] # !send_state[1] # !send_state[0];


--A1L262 is txd_buf[3]~1757 at LC_X15_Y4_N4
--operation mode is normal

A1L262 = state_tras[2] & (!state_tras[1] # !state_tras[0]) # !state_tras[2] & (state_tras[1]);


--A1L8 is Select~3001 at LC_X15_Y4_N3
--operation mode is normal

A1L8 = A1L951 & (A1L262) # !A1L951 & trasstart & (!A1L3);


--A1L9 is Select~3003 at LC_X15_Y6_N5
--operation mode is normal

A1L9 = state_tras[3] & (!state_tras[1] & !state_tras[2]) # !state_tras[3] & (state_tras[0] # state_tras[1] # state_tras[2]);


--A1L252 is trasstart~39 at LC_X15_Y5_N5
--operation mode is normal

A1L252 = key_entry2 & (!A1L9);


--A1L51 is add~1062 at LC_X15_Y5_N6
--operation mode is normal

A1L51 = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0];


--A1L332 is send_state[2]~0 at LC_X14_Y5_N8
--operation mode is normal

A1L332 = key_entry2 & state_tras[2] & A1L51 & A1L432;


--A1L532 is send_state[2]~97 at LC_X14_Y5_N9
--operation mode is normal

A1L532 = send_state[0] & send_state[1] & A1L332;


--A1L632 is send_state[2]~98 at LC_X13_Y5_N8
--operation mode is normal

A1L632 = send_state[0] & (A1L332);


--A1L01 is Select~3005 at LC_X15_Y6_N4
--operation mode is normal

A1L01 = state_tras[1] & state_tras[0];


--A1L11 is Select~3006 at LC_X15_Y6_N1
--operation mode is normal

A1L11 = state_tras[3] & (state_tras[1] & (!state_tras[2] # !state_tras[0]) # !state_tras[1] & (state_tras[2]));


--A1L21 is Select~3007 at LC_X15_Y6_N3
--operation mode is normal

A1L21 = state_tras[0] & (state_tras[1] $ !state_tras[2] # !state_tras[3]);


--A1L31 is Select~3008 at LC_X15_Y6_N8
--operation mode is normal

A1L31 = A1L11 & A1L51 & !A1L21 # !A1L11 & (A1L21);


--div_reg[2] is div_reg[2] at LC_X13_Y9_N4
--operation mode is arithmetic

div_reg[2]_lut_out = div_reg[2] $ (!A1L89);
div_reg[2] = DFFEAS(div_reg[2]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L101 is div_reg[2]~342 at LC_X13_Y9_N4
--operation mode is arithmetic

A1L101 = CARRY(div_reg[2] & (!A1L99));


--div_reg[3] is div_reg[3] at LC_X13_Y9_N5
--operation mode is arithmetic

div_reg[3]_carry_eqn = A1L101;
div_reg[3]_lut_out = div_reg[3] $ (div_reg[3]_carry_eqn);
div_reg[3] = DFFEAS(div_reg[3]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L301 is div_reg[3]~346 at LC_X13_Y9_N5
--operation mode is arithmetic

A1L301_cout_0 = !A1L101 # !div_reg[3];
A1L301 = CARRY(A1L301_cout_0);

--A1L401 is div_reg[3]~346COUT1_424 at LC_X13_Y9_N5
--operation mode is arithmetic

A1L401_cout_1 = !A1L101 # !div_reg[3];
A1L401 = CARRY(A1L401_cout_1);


--div_reg[0] is div_reg[0] at LC_X13_Y9_N2
--operation mode is arithmetic

div_reg[0]_lut_out = !div_reg[0];
div_reg[0] = DFFEAS(div_reg[0]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L59 is div_reg[0]~350 at LC_X13_Y9_N2
--operation mode is arithmetic

A1L59_cout_0 = div_reg[0];
A1L59 = CARRY(A1L59_cout_0);

--A1L69 is div_reg[0]~350COUT1_420 at LC_X13_Y9_N2
--operation mode is arithmetic

A1L69_cout_1 = div_reg[0];
A1L69 = CARRY(A1L69_cout_1);


--div_reg[1] is div_reg[1] at LC_X13_Y9_N3
--operation mode is arithmetic

div_reg[1]_lut_out = div_reg[1] $ (A1L59);
div_reg[1] = DFFEAS(div_reg[1]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L89 is div_reg[1]~354 at LC_X13_Y9_N3
--operation mode is arithmetic

A1L89_cout_0 = !A1L59 # !div_reg[1];
A1L89 = CARRY(A1L89_cout_0);

--A1L99 is div_reg[1]~354COUT1_422 at LC_X13_Y9_N3
--operation mode is arithmetic

A1L99_cout_1 = !A1L69 # !div_reg[1];
A1L99 = CARRY(A1L99_cout_1);


--A1L061 is reduce_nor~319 at LC_X12_Y9_N9
--operation mode is normal

A1L061 = div_reg[2] # div_reg[3] # !div_reg[0] # !div_reg[1];


--div_reg[4] is div_reg[4] at LC_X13_Y9_N6
--operation mode is arithmetic

div_reg[4]_carry_eqn = (!A1L101 & A1L301) # (A1L101 & A1L401);
div_reg[4]_lut_out = div_reg[4] $ (!div_reg[4]_carry_eqn);
div_reg[4] = DFFEAS(div_reg[4]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L601 is div_reg[4]~358 at LC_X13_Y9_N6
--operation mode is arithmetic

A1L601_cout_0 = div_reg[4] & (!A1L301);
A1L601 = CARRY(A1L601_cout_0);

--A1L701 is div_reg[4]~358COUT1_426 at LC_X13_Y9_N6
--operation mode is arithmetic

A1L701_cout_1 = div_reg[4] & (!A1L401);
A1L701 = CARRY(A1L701_cout_1);


--div_reg[5] is div_reg[5] at LC_X13_Y9_N7
--operation mode is arithmetic

div_reg[5]_carry_eqn = (!A1L101 & A1L601) # (A1L101 & A1L701);
div_reg[5]_lut_out = div_reg[5] $ div_reg[5]_carry_eqn;
div_reg[5] = DFFEAS(div_reg[5]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L901 is div_reg[5]~362 at LC_X13_Y9_N7
--operation mode is arithmetic

A1L901_cout_0 = !A1L601 # !div_reg[5];
A1L901 = CARRY(A1L901_cout_0);

--A1L011 is div_reg[5]~362COUT1_428 at LC_X13_Y9_N7
--operation mode is arithmetic

A1L011_cout_1 = !A1L701 # !div_reg[5];
A1L011 = CARRY(A1L011_cout_1);


--div_reg[6] is div_reg[6] at LC_X13_Y9_N8
--operation mode is arithmetic

div_reg[6]_carry_eqn = (!A1L101 & A1L901) # (A1L101 & A1L011);
div_reg[6]_lut_out = div_reg[6] $ (!div_reg[6]_carry_eqn);
div_reg[6] = DFFEAS(div_reg[6]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L211 is div_reg[6]~366 at LC_X13_Y9_N8
--operation mode is arithmetic

A1L211_cout_0 = div_reg[6] & (!A1L901);
A1L211 = CARRY(A1L211_cout_0);

--A1L311 is div_reg[6]~366COUT1_430 at LC_X13_Y9_N8
--operation mode is arithmetic

A1L311_cout_1 = div_reg[6] & (!A1L011);
A1L311 = CARRY(A1L311_cout_1);


--div_reg[7] is div_reg[7] at LC_X13_Y9_N9
--operation mode is arithmetic

div_reg[7]_carry_eqn = (!A1L101 & A1L211) # (A1L101 & A1L311);
div_reg[7]_lut_out = div_reg[7] $ div_reg[7]_carry_eqn;
div_reg[7] = DFFEAS(div_reg[7]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L611 is div_reg[7]~370 at LC_X13_Y9_N9
--operation mode is arithmetic

A1L611 = CARRY(!A1L311 # !div_reg[7]);


--A1L161 is reduce_nor~320 at LC_X12_Y9_N4
--operation mode is normal

A1L161 = div_reg[4] # div_reg[6] # div_reg[7] # div_reg[5];


--div_reg[9] is div_reg[9] at LC_X14_Y9_N1
--operation mode is arithmetic

div_reg[9]_carry_eqn = (!A1L611 & A1L811) # (A1L611 & A1L911);
div_reg[9]_lut_out = div_reg[9] $ div_reg[9]_carry_eqn;
div_reg[9] = DFFEAS(div_reg[9]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L121 is div_reg[9]~374 at LC_X14_Y9_N1
--operation mode is arithmetic

A1L121_cout_0 = !A1L811 # !div_reg[9];
A1L121 = CARRY(A1L121_cout_0);

--A1L221 is div_reg[9]~374COUT1_434 at LC_X14_Y9_N1
--operation mode is arithmetic

A1L221_cout_1 = !A1L911 # !div_reg[9];
A1L221 = CARRY(A1L221_cout_1);


--div_reg[10] is div_reg[10] at LC_X14_Y9_N2
--operation mode is arithmetic

div_reg[10]_carry_eqn = (!A1L611 & A1L121) # (A1L611 & A1L221);
div_reg[10]_lut_out = div_reg[10] $ !div_reg[10]_carry_eqn;
div_reg[10] = DFFEAS(div_reg[10]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L421 is div_reg[10]~378 at LC_X14_Y9_N2
--operation mode is arithmetic

A1L421_cout_0 = div_reg[10] & !A1L121;
A1L421 = CARRY(A1L421_cout_0);

--A1L521 is div_reg[10]~378COUT1_436 at LC_X14_Y9_N2
--operation mode is arithmetic

A1L521_cout_1 = div_reg[10] & !A1L221;
A1L521 = CARRY(A1L521_cout_1);


--div_reg[11] is div_reg[11] at LC_X14_Y9_N3
--operation mode is arithmetic

div_reg[11]_carry_eqn = (!A1L611 & A1L421) # (A1L611 & A1L521);
div_reg[11]_lut_out = div_reg[11] $ (div_reg[11]_carry_eqn);
div_reg[11] = DFFEAS(div_reg[11]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L721 is div_reg[11]~382 at LC_X14_Y9_N3
--operation mode is arithmetic

A1L721_cout_0 = !A1L421 # !div_reg[11];
A1L721 = CARRY(A1L721_cout_0);

--A1L821 is div_reg[11]~382COUT1_438 at LC_X14_Y9_N3
--operation mode is arithmetic

A1L821_cout_1 = !A1L521 # !div_reg[11];
A1L821 = CARRY(A1L821_cout_1);


--div_reg[8] is div_reg[8] at LC_X14_Y9_N0
--operation mode is arithmetic

div_reg[8]_carry_eqn = A1L611;
div_reg[8]_lut_out = div_reg[8] $ !div_reg[8]_carry_eqn;
div_reg[8] = DFFEAS(div_reg[8]_lut_out, GLOBAL(clk), VCC, , , , , A1L411, );

--A1L811 is div_reg[8]~386 at LC_X14_Y9_N0
--operation mode is arithmetic

A1L811_cout_0 = div_reg[8] & !A1L611;
A1L811 = CARRY(A1L811_cout_0);

--A1L911 is div_reg[8]~386COUT1_432 at LC_X14_Y9_N0
--operation mode is arithmetic

A1L911_cout_1 = div_reg[8] & !A1L611;
A1L911 = CARRY(A1L911_cout_1);


--A1L261 is reduce_nor~321 at LC_X14_Y9_N8