serial.map.rpt

串口通讯 verilog CPLD EPM1270 源代码

; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 78    ;
; Number of registers using Synchronous Clear  ; 40    ;
; Number of registers using Synchronous Load   ; 5     ;
; Number of registers using Asynchronous Clear ; 39    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 51    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; txd_reg                                ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |serial|div_reg[6]         ;
; 4:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |serial|cnt_delay[12]      ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |serial|state_rec[0]       ;
; 14:1               ; 3 bits    ; 27 LEs        ; 6 LEs                ; 21 LEs                 ; Yes        ; |serial|txd_buf[6]         ;
; 21:1               ; 3 bits    ; 42 LEs        ; 18 LEs               ; 24 LEs                 ; Yes        ; |serial|txd_buf[3]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |serial ;
+----------------+------------------+------------------------------------+
; Parameter Name ; Value            ; Type                               ;
+----------------+------------------+------------------------------------+
; div_par        ; 0000000100000100 ; Binary                             ;
+----------------+------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/串口/serial.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:25:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial
Info: Found 1 design units, including 1 entities, in source file serial.v
    Info: Found entity 1: serial
Info: Elaborating entity "serial" for the top level hierarchy
Warning: Verilog HDL assignment warning at serial.v(57): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(64): truncated value with size 32 to match size of target (20)
Warning: Verilog HDL assignment warning at serial.v(65): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(69): truncated value with size 32 to match size of target (20)
Warning: Verilog HDL assignment warning at serial.v(72): truncated value with size 32 to match size of target (20)
Warning: Verilog HDL assignment warning at serial.v(73): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(78): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(85): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(88): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(91): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(99): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at serial.v(102): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at serial.v(104): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at serial.v(111): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(120): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(122): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(128): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(130): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(136): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(138): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(144): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(146): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(152): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(153): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(154): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at serial.v(155): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(156): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(157): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(162): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(170): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(173): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(174): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(178): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(179): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(186): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(193): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(200): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(207): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(214): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(221): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(228): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(235): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(240): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(242): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(247): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(248): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at serial.v(249): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(264): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at serial.v(270): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(271): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(282): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(283): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(284): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at serial.v(285): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(286): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(287): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(294): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(295): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(296): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(299): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at serial.v(305): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(310): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at serial.v(311): truncated value with size 32 to match size of target (1)
Warning: Reduced register "txd_buf[7]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at VCC
    Warning: Pin "en[2]" stuck at VCC
    Warning: Pin "en[3]" stuck at VCC
    Warning: Pin "en[4]" stuck at VCC
    Warning: Pin "en[5]" stuck at VCC
    Warning: Pin "en[6]" stuck at VCC
    Warning: Pin "en[7]" stuck at VCC
    Warning: Pin "seg_data[0]" stuck at VCC
    Warning: Pin "lowbit" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 210 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 18 output pins
    Info: Implemented 188 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 75 warnings
    Info: Processing ended: Sat Feb 18 13:25:15 2006
    Info: Elapsed time: 00:00:11