serial.tan.summary

串口通讯 verilog CPLD EPM1270 源代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.527 ns
From           : rst
To             : cnt_delay[15]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.431 ns
From           : rxd_buf[6]
To             : seg_data[4]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.963 ns
From           : rxd
To             : rxd_reg1
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 101.73 MHz ( period = 9.830 ns )
From           : cnt_delay[11]
To             : cnt_delay[19]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : key_entry1
To             : key_entry2
From Clock     : clk
To Clock       : clk
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

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