traffic.tan.rpt

模拟交通灯 verilog CPLD EPM1270 源代码

; N/A   ; None         ; 19.011 ns  ; first[3]   ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.989 ns  ; second[2]  ; dataout[5] ; clk        ;
; N/A   ; None         ; 18.966 ns  ; en_xhdl[0] ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.936 ns  ; first[0]   ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.912 ns  ; first[1]   ; dataout[6] ; clk        ;
; N/A   ; None         ; 18.897 ns  ; first[1]   ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.894 ns  ; first[2]   ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.886 ns  ; second[1]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.865 ns  ; first[3]   ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.862 ns  ; first[1]   ; dataout[2] ; clk        ;
; N/A   ; None         ; 18.794 ns  ; first[0]   ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.794 ns  ; second[2]  ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.782 ns  ; state[0]   ; lightG[3]  ; clk        ;
; N/A   ; None         ; 18.782 ns  ; state[0]   ; lightG[1]  ; clk        ;
; N/A   ; None         ; 18.750 ns  ; second[2]  ; dataout[2] ; clk        ;
; N/A   ; None         ; 18.681 ns  ; second[2]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.671 ns  ; first[1]   ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.651 ns  ; second[3]  ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.643 ns  ; second[3]  ; dataout[2] ; clk        ;
; N/A   ; None         ; 18.600 ns  ; second[0]  ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.512 ns  ; second[2]  ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.497 ns  ; second[3]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.458 ns  ; second[0]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.404 ns  ; state[1]   ; lightG[3]  ; clk        ;
; N/A   ; None         ; 18.404 ns  ; state[1]   ; lightG[1]  ; clk        ;
; N/A   ; None         ; 18.351 ns  ; second[3]  ; dataout[4] ; clk        ;
; N/A   ; None         ; 18.147 ns  ; state[0]   ; lightG[2]  ; clk        ;
; N/A   ; None         ; 18.147 ns  ; state[0]   ; lightG[0]  ; clk        ;
; N/A   ; None         ; 18.110 ns  ; state[0]   ; lightR[3]  ; clk        ;
; N/A   ; None         ; 17.769 ns  ; state[1]   ; lightG[2]  ; clk        ;
; N/A   ; None         ; 17.769 ns  ; state[1]   ; lightG[0]  ; clk        ;
; N/A   ; None         ; 17.741 ns  ; state[1]   ; lightY[3]  ; clk        ;
; N/A   ; None         ; 17.741 ns  ; state[1]   ; lightY[1]  ; clk        ;
; N/A   ; None         ; 17.733 ns  ; state[1]   ; lightR[3]  ; clk        ;
; N/A   ; None         ; 17.706 ns  ; state[1]   ; lightY[2]  ; clk        ;
; N/A   ; None         ; 17.706 ns  ; state[1]   ; lightY[0]  ; clk        ;
; N/A   ; None         ; 17.560 ns  ; state[0]   ; lightR[2]  ; clk        ;
; N/A   ; None         ; 17.560 ns  ; state[0]   ; lightR[1]  ; clk        ;
; N/A   ; None         ; 17.560 ns  ; state[0]   ; lightR[0]  ; clk        ;
; N/A   ; None         ; 17.313 ns  ; state[0]   ; lightY[3]  ; clk        ;
; N/A   ; None         ; 17.313 ns  ; state[0]   ; lightY[1]  ; clk        ;
; N/A   ; None         ; 17.278 ns  ; state[0]   ; lightY[2]  ; clk        ;
; N/A   ; None         ; 17.278 ns  ; state[0]   ; lightY[0]  ; clk        ;
; N/A   ; None         ; 17.183 ns  ; state[1]   ; lightR[2]  ; clk        ;
; N/A   ; None         ; 17.183 ns  ; state[1]   ; lightR[1]  ; clk        ;
; N/A   ; None         ; 17.183 ns  ; state[1]   ; lightR[0]  ; clk        ;
; N/A   ; None         ; 17.064 ns  ; en_xhdl[0] ; en[0]      ; clk        ;
; N/A   ; None         ; 16.902 ns  ; en_xhdl[1] ; en[1]      ; clk        ;
+-------+--------------+------------+------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 11:21:35 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "div_cnt[15]" as buffer
    Info: Detected ripple clock "div_cnt[24]" as buffer
Info: Clock "clk" has Internal fmax of 125.49 MHz between source register "first[1]" and destination register "second[1]" (period= 7.969 ns)
    Info: + Longest register to register delay is 7.260 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N6; Fanout = 5; REG Node = 'first[1]'
        Info: 2: + IC(0.923 ns) + CELL(0.914 ns) = 1.837 ns; Loc. = LC_X11_Y7_N8; Fanout = 6; COMB Node = 'reduce_or~0'
        Info: 3: + IC(1.999 ns) + CELL(0.511 ns) = 4.347 ns; Loc. = LC_X10_Y7_N5; Fanout = 4; COMB Node = 'second[3]~1006'
        Info: 4: + IC(1.852 ns) + CELL(1.061 ns) = 7.260 ns; Loc. = LC_X11_Y6_N0; Fanout = 6; REG Node = 'second[1]'
        Info: Total cell delay = 2.486 ns ( 34.24 % )
        Info: Total interconnect delay = 4.774 ns ( 65.76 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 10.984 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(4.679 ns) + CELL(1.294 ns) = 7.105 ns; Loc. = LC_X14_Y3_N7; Fanout = 11; REG Node = 'div_cnt[24]'
            Info: 3: + IC(2.961 ns) + CELL(0.918 ns) = 10.984 ns; Loc. = LC_X11_Y6_N0; Fanout = 6; REG Node = 'second[1]'
            Info: Total cell delay = 3.344 ns ( 30.44 % )
            Info: Total interconnect delay = 7.640 ns ( 69.56 % )
        Info: - Longest clock path from clock "clk" to source register is 10.984 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(4.679